Assessment of image placement errors induced in electron projection lithography masks by chuckingProximity effect correction using pattern shape modification and area density map for electron-beam projection lithography J.A high-performance membrane mask for electron projection lithography ͑EPL͒ systems is proposed. The design and material selection of the mask described here were carefully executed by considering not only the lithographic performance but also various properties. The mask described in this article consists of a 600-nm-thick diamond-like carbon ͑DLC͒ scatter on a DLC membrane 30-60 nm thick. The optimum thicknesses are obtained by calculating angular distributions of the transmitted electrons by our in-house Monte Carlo simulator. It is expected to have an electron transmission of up to 80% and a beam contrast of 100% with an appropriate limiting aperture. A 1-mm-sq membrane of thickness of down to 30 nm could be successfully prepared. The high-performance membrane mask can obtain high resolution and high throughput of the EPL systems simultaneously.
A new method for proximity effect correction, suitable for large-field electron-beam (EB)
projection lithography with high accelerating voltage, such as SCALPEL and PREVAIL in the
case where a stencil mask is used, is discussed. In this lithography, a large-field is exposed by
the same dose, and thus, the dose modification method, which is used in the variable-shaped
beam and the cell projection methods, cannot be used in this case. In this study, we report on
development of a new proximity effect correction method which uses a pattern modified stencil
mask suitable for high accelerating voltage and large-field EB projection lithography. In order
to obtain the mask bias value, we have investigated linewidth reduction, due to the proximity
effect, in the peripheral memory cell area, and found that it could be expressed by a simple
function and all the correction parameters were easily determined from only the mask pattern
data. The proximity effect for the peripheral array pattern could also be corrected by
considering the pattern density. Calculated linewidth deviation was 3% or less for a 0.07-µm-L/S memory cell pattern and 5% or less for a 0.14-µm-line and 0.42-µm-space peripheral array
pattern, simultaneously.
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