Neural networks (NN) have been widely used for electricity forecasting, but some difficulties are still found. One of those difficulties is in choosing the optimal network parameter, which are strongly important to obtain accurate result. "Trial and error" commonly used to set the parameter is ineffective in terms of processing time and the accuracy. In this paper, Taguchi method is employed to optimize the accuracy of NN based prediction. This hybrid approach results in the optimal network parameters. Those are: 1 for the history length, 1 day for sampling time, and 8 nodes for hidden neurons. The method is used to predict electricity consumption in Universiti Teknologi PETRONAS (UTP), Malaysia. From the preliminary results it is found that the combined method seems to be a convincing approach.
Abstract-Until now, the external memory architectures of the two-dimensional discrete wavelet transform (2-D DWT) such as the external RAM and the memory between DWT unit and compression unit, call it, subband memory, which are in need of architecting, have been overlooked in the literature. Since, 2-D DWT memory architectures are equally important as DWT processor architectures commonly covered in the literature, in this paper, two novel VLSI memory architectures for lifting-based 5/3 and 9/7 DWT are proposed. The first proposed memory architecture, the RAM, is read and written by DWT unit only, whereas, the second proposed memory architecture, the subband memory, is written by DWT unit and is read by compression unit.Index Terms-DWT memory architecture, LL-RAM, subband memory, lifting scheme, and VLSI architecture I. INTRODUCTIONThe 2-D DWT considered in this paper is part of a compression system. The general structure of a compression system is shown in Fig. 1. The DWT unit generally consists of a row-processor (RP) and a column-processor (CP) [1,2]. RP reads LL-RAM, while CP writes into LL-RAM and subband memory.DWT decomposes an NxM image into subands, as shown in Fig. 2 for 3 decomposition levels [7]. These subbands must be stored by DWT unit in a memory such that they can be manipulated effectively by compression unit for compression purposes. Therefore, a memory architecture, which allows DWT unit to perform efficiently both, reads and writes and compression unit to perform reads is necessary. Fig. 2 shows that the first decomposition generates 4 subbands labeled HL1, HH1, LH1, and LL1. The coefficients of the first 3 subbands would be stored in a memory, call it subband memory, which would contain memory blocks labeled HL1, HH1, and LH1. The compression unit can then read the 3 subbands and compress each independently. While the LL1 subband would be stored in another memory, call it, LL-RAM or just RAM, for further decompositions.The second decomposition generates 4 subbands, labeled HL2, HH2, LH2, LL2, by reading subband LL1 coefficients stored in the LL-RAM. The coefficients of the 3 subbands HL2, HH2, and LH2 would be stored also in the subband memory blocks labeled HL2, HH2, and LH2, while subband LL2 would be stored in the RAM for further decomposition.In the discussion above, two memory components haveThe authors are with the Electrical and Electronic Engineering Department, Universiti Teknologi PETRONAS, Perak, Tronoh, Malaysia (emails: kokois12@hotmail.com, herman_agustiawan@petronas.com.my).been identified, the LL-RAM and the subband memory that need to be designed such that DWT unit can perform effectively both read and write operations in the LL-RAM and write only into subband memory, while compression unit can read subband memory. This paper is organized as follows. In sections II and III the proposed external RAM and subband memory architectures are presented. Conclusions are given in section IV. The LL-RAM is used by the DWT unit to store the coefficients of the LL subband that it generat...
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In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-D DWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed parallel architectures is that the total temporary line buffer (TLB) does not increase from that of the single pipelined architecture proposed by Ibrahim et al. when degree of parallelism is increased.
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