In this paper, issues related to the optimization of superconducting passive interconnects are discussed. Results of the microwave optimization of bends, via connections and crossings of superconducting microstrip lines (SMSLs) are reported. The optimum design of the SMSL cross gives more than 95% of transmission and can be well used in a two-bus cross design with up to 14 signal wires. The results have been confirmed by time-domain simulations and measurements.
The multiply-accumulate unit (MAC) is a central component of a successive interference canceller, an advanced receiver for W-CDMA base stations. A 4 × 4 two's complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL, and maximum performance is equal to 24 GMACS (giga-multiply-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate the data dependence of the clock propagation speed and reduce the number of Josephson junctions in clock lines. The 4 × 4 bit MAC has been designed for the HYPRES 4.5 kA cm −2 process and its components have been experimentally tested at low frequency: the 5-bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of ±18%, and the 4 × 4 parallel multiplier had margins equal to ±2%.
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