The device behavior of a Stacked Ferroelectric Heterojunction Tunnel FET (Fe-HTFET) on BOX substrate is investigated in this paper. In a stacked gate configuration, Si-doped HfO2 was taken as the ferroelectric material over an oxide layer (gate dielectric). Higher drive current and reduced sub-threshold swings (SS) may be achieved by using a silicon doped HfO2 that amplifies the given gate bias. The effect of various electrical parameters has been investigated by changing the geometric dimensions of the proposed device. The dimensional parameters have been optimized after extensive simulations. The proposed Fe-HTFET simulations and results show that this structure boosts performance significantly and could be considered a good contender for ultra-low-power applications. In order to investigate the performance of the proposed Fe-HTFET, 2-D simulations have been done using Sentaurus TCAD tool.
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