A new method of designing reversible logic circuits which can be adopted by any synthesis technique to produce parity preserving reversible circuits based on Multiple Controlled Tofolli gates is proposed. The designed circuit using proposed methodology is easily testable by checking the input and output parity. A set of benchmark circuits and corresponding testable designs are implemented. The results under testable designs show an average reduction of 32% in operating cost as compared to prior work.Introduction: Miniaturisation does not seem to be promising method in the development of compact electronic devices due to the breakdown of Dennard scaling [1]. Reversible logic is one of the foregrounds to meet the destiny of future electronics based on quantum computation. These circuits guarantee nearly energy free computation by preventing loss of information in the form of heat as in irreversible logic circuits [2, 3]. The researchers are at par with the latest innovations in this area to develop combinational and sequential logic circuit designs which are based on different gate libraries. A reversible gate library defines a set of basic reversible gates which are used individually or in combination to synthesise a reversible circuit in the manner they produce efficient results in terms on performance parameters. Multiple controlled Tofolli (MCT) often called as k-CNOT gates, multiple controlled Fredkin (MCF), NOT-CNOT-Tofolli (NCT) are widely used gate libraries [4, 5] and the parameters include gate cost, quantum cost, ancilla input and garbage output. These parameters are directly related to the power dissipation and the size which well defines the operating cost of any designing methodology [6]. Parity checking is found most favourable method of testing reversible logic circuits because they perform fully controllable and observable operations due to the ability of producing bijective functions. Several online testing methods base on parity checking have been proposed for their recognition by the detection of single/multiple bit faults as any type of fault occurrence will result in change of single/multiple values of bits on the wires of the circuit [6]. These methods can be categorised as designing using novel gates [7,8] and designing using a modification of standard circuits or gates [6,9,10]. In this work, a new method of designing k-CNOT-based reversible circuit is proposed, which produces parity preserving circuits rather than converting a standard circuit by means of novel gates or any modification in order to incorporate testability feature. The testability of these circuits can be achieved more easily by checking the input and output parity without any algorithm formulation under single bit fault detection. The circuits produced are incorporated with high testability which can be adopted by any synthesis method to induce online testability features.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.