Abstract. In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.
Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection) codes will be limited. In order to cure this dilemma, efficient fault scrambling techniques are proposed in this paper. Unlike the fixed constituting memory cells of a codeword in the conventional EDAC schemes, we try to reconstruct the memory cells of codewords such that each codeword consists of at most one faulty cell. The corresponding scrambling circuits are also proposed and a simulator is developed to evaluate the repair rates and hardware overhead. According to experimental results, the repair rates can be improved significantly with negligible hardware overhead.
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