Time division multiple access (TDMA)-based medium access control (MAC) protocols can guarantee quality of service (QoS) in wireless environments. However, in an environment where multihop packet transmissions are necessary for real-time communications, each node may experience the well-known queuing delay. This queuing delay increases multihop packet transmission delay, resulting in not meeting the delay bound of real-time applications in multihop wireless networks. This article first introduces two kinds of queuing delays that can occur in multihop wireless networks. Then, this article proposes a new delay-efficient TDMA-based distributed scheduling scheme to eliminate the secondary queuing delay. For the performance analysis of the proposed scheme, the scheduling overhead is first evaluated in terms of power consumption. Next, the multihop packet transmission delay of the proposed scheduling scheme is derived and validated through a simulation, before comparing the result with that of the conventional minimum length scheduling scheme which employs distance-2 graph coloring. According to the simulation and analysis results, for a deterministic packet arrival, the proposed scheme works well irrespective of the packet interarrival rate and outperforms the conventional graph coloring. However, in case of a non-deterministic packet arrival, the multihop packet transmission delay of the proposed scheme is slightly higher than that of the conventional graph coloring because the probability that each node has more than two packets increases at the beginning of the frame. However, the multihop packet transmission delay of the conventional graph coloring is intolerable when the packet interarrival rate is high.
In this paper, we survey the works related to the system architecture of avionics and extract characteristics from the related works. On the basis of the investigation, we propose an integrated modular avionics (IMA) architecture that can be used for current avionic upgrades and future avionic developments based on the IMA Core system. To verify the feasibility of the proposed IMA architecture, we have developed the prototype of the IMA Core system that consists of both the common hardware module and the IMA software. It was verified that the developed prototype with the common hardware module contributes to the improvement of maintainability because it can save the time and expenses for the development and can reduce the number of types of hardware modules when compared with Federated architecture. It was also confirmed that the developed prototype can save not only overall system weight, size, and power consumption but also the number of hardware types because the IMA software can support the integrated processing where the single processing hardware module can process multiple software applications.
Built-In-Test(hereafter: BIT) is necessary functionality for aircraft flight safety and it requires a high failure detection capacity of more than 95 % in the case of avionics equipment. The BIT coverage analysis is needed to make sure that BIT meets its fault diagnosis capability. FMECA is used a lot of for the BIT coverage analysis. However, in this paper, the BIT coverage analysis based on electronic components is introduced to minimize the analytical error. Further, by applying the failure mode of the electronic components and excluding electronic components that do not affect flight safety, the BIT coverage analysis can be more accurate. Finally, BIT demo was performed and it was confirmed that the performance of the actual BIT matches the analysis of BIT performance.
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