Series connection of power cells in asymmetrical cascaded configurations helps to cancel redundant output levels and maximise the number of different levels generated by the inverter. A new configuration of three-phase multilevel asymmetrical cascaded voltage source inverter is presented. This structure consists of series-connected sub-multilevel inverters blocks. The number of utilised switches, insulated gate driver circuits, voltage standing on switches, installation area and cost are considerably reduced. Cascaded-cell DC voltages in each inverter leg form an arithmetic sequence with common difference of E. With the selected inverter DC sources, high-frequency pulse-width modulation (PWM) control methods can be effectively applied without loss of modularity. Low-frequency and sinusoidal PWM techniques were successfully applied. Hence, high flexibility in the modulation of the proposed inverter is demonstrated. The prototype of the suggested inverter was manufactured and the obtained simulation and hardware results ensured the feasibility of the configuration, and the compatibility of both modulation techniques was accurately noted. Lastly, the semiconductor losses in the converter were calculated using simulation models. Based on the analysis of the total power losses, the proposed inverter provided high efficiency at different operating conditions.

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

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Multilevel inverters are becoming increasingly popular for high and medium power applications. The diode clamped multilevel inverter (DCMLI) is an attractive high voltage multilevel inverter due to its robustness. The deviating voltage at the neutral point remains always a distracting feature in NPC inverter. For this reason DC link capacitors voltage balancing is crucial task in such configuration. The focus of this paper is a three-level three-phase neutral point clamped inverter. A modulation technique that balances the voltage in the DC link capacitors is presented. A Feedback voltage control method has been employed and a space vector pulse width modulation (SVPWM) is used as flexible technique to generate pulses that maintain a balanced DC link. The balancing is limited to an acceptable level without the use of the external active capacitor balancing circuit. To validate the effectiveness of the proposed method both simulation and experimental results are provided.

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This paper introduces a new three-phase three-level voltage source inverter. The proposed topology constitutes the conventional three-phase two-level inverter with three bidirectional switches. For purpose of generating the appropriate switching gate signals, two different commutation strategies are suggested and analyzed. A comparison between both strategies in terms of power losses and efficiency are presented. To ensure the feasibility of the proposed configuration with its suggested commutation strategies, the prototype of the proposed inverter was manufactured and the experimental results are given.