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SUMMARY This paper deals with an improved decoupling control of the current components applied to three‐phase modular multilevel converter (MMC) via rotating d‐q frame theory based on the mathematical model of the system. In order to apply independent controllers for the two axes in d‐q coordinates, the impact of the q‐axis on the d‐axis component and vice versa has to be removed. This is done by creating a decoupling block consisting of modified coupling terms. The feed‐forward ac‐side voltages compensation can effectively reduce any harmonic disturbance of the load side. Furthermore, we employed the strategy to reduce the capacitor voltages variation in each arm. A comparison of simulation results for both existing and improved decoupling current control algorithms using a (6.6 kV, 6 MW) induction motor drive verifies the superior performance of the proposed controller especially for good current reference tracking and disturbance rejection properties despite the variations in the system parameters. Copyright © 2013 John Wiley & Sons, Ltd.

This study presents a detailed time domain model of a modular multilevel converter (MMC) to provide an alternative form of evaluation of the converter dynamic performance, for example, during AC or DC fault conditions. The purpose of the model is to accurately reflect the converter behaviour to be used in control systems design. It can also be beneficial to predict the steady state or transient state of the converter with fixed or variable inputs. In an MMC, the capacitor voltages are modulated using pulse-width modulation (PWM) to fabricate a sinusoidal output voltage. With time, and because of the PWM action, the capacitors get charged or discharged. Therefore the circuit behaves as a time-variant circuit. The analysis is based on the equivalent circuit derived from the converter differential expressions at any time instant in a piecewise fashion. The usefulness and accuracy of the theoretical study is validated for the three-phase MMC topology by simulation results with respect to normal operation, start-up process, cell short-circuit fault, line-to-ground and DC-side fault conditions. Experimental tests are carried out through a scaleddown laboratory prototype.

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