New and stronger video compression standard was developed during the last years, called H.265/HEVC (High Efficiency Video Coding). This standard has undergone several improvements compared to H.264/AVC (Advanced Video Coding). In intra prediction block, 33 directional intra prediction modes were included in H.265 to have an efficient coding instead of 8 modes that were used in H.264 in addition to planar and DC modes, which has generated computational complexities in the new standard. Therefore one of the most issues for embedded implementation of HEVC is time reduction of the encoding process. In this paper, an embedded implementation of a fast intra prediction algorithm is performed on ARM processors under the embedded Linux Operating System. Experimental results included the comparison between the original HM16.7 and the proposed algorithm show that the encoding time was reduced by an average of 61.5% with an increase of 1.19 in the bit rate and a small degradation in the PSNR of 0.05%.
Summary
Statistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).
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