FPGA is among the most successful digital IC. Though initially targeted for prototyping, but received more attention even in small volume production. However, that success is under threat since Silicon is reaching physical limitations. According to ITRS, towards the sub-nanometer regime, various second-order effects affect the functionality and reduces the performance of the device. Research on alternative materials indicates that Graphene is the most attractive candidate, and field-effect transistors using Graphene Nano-Ribbons Field Effect Transistors (GNRFETs) are promising because of their excellent properties. Toward all-Graphene microelectronics, and due to FPGA position in digital design, Graphene-based FPGA needs to be designed, analyzed, and evaluated. This paper explores FPGA design based on GNRFETs. It studies the design and characterization of all parts of a Graphene-based simple FPGA which could be a configurable logic structure for future microelectronics. It covers main parts, by design and characterization of Configurable Logic Block, routing switch, and I/O block, all based on GNRFET. The results as 47 ps delay for output and 23 ps for input proves feasibility, and indicate that proposed C-FPGA designs are much faster than conventional silicon-based counterparts. Power Delay Product of proposed CLB element is 5.3 times lesser than those of silicon counterparts.
Silicon-based electronics is going to face limitations and need to be replaced by alternative materials. Carbon is one of the most probable candidates. In every digital IC, Input/Output block is needed to interface the internal logic with the off-chip world and is a crucial for each IC. Toward all-carbon electronics, I/O block has to be redesigned and characterized. In this paper, an optimized and low-area graphene-based I/O block is proposed. A novel design algorithm is developed to size the graphene-based buffer chain, which is capable of driving a large off-chip load. Besides the buffer chain, required sub-circuits such as level-shifter, Schmitttrigger, tristate buffer, flip-flop, and MUX are also designed to build a complete I/O block. Using effective modelling and intensive simulation, blocks designed, modelled, and characterized. Results indicate that graphene-based I/O block is feasible. The propagation delay is reduced by 5.2 times and occupied area reduced 2/3 compared with the silicon-based I/O block. The proposed I/O block can drive capacitive load as large as 50 pF, which is higher than the silicon-based I/O. Using GNR, a layout is presented for I/O block. It is shown that the proposed I/O block can communicate with an efficient speed while it has Nano-scale size.
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