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We have investigated a Hf-based CMOSFET fabrication method that would enable the high performance and low gate leakage current that are required for the 65-nm-node CMOS devices. To suppress the gate leakage in a gate stack with an equivalent oxide thickness (EOT) of 1.2 nm, the upper layer of HfSiO film was thickened and nitrided. The nitridation improves the dielectric constant, allowing the use of a thicker HfSiO layer. The mobility was improved by lightly nitriding the bottom SiO2 interface layer, which suppresses the interfacial trap generation. Such techniques enabled us to achieve a good EOT vs I g relationships. The I g at an EOT of 1.2 nm was reduced by three orders of magnitude as compared with that with a SiO2 gate insulator. High mobilities, 87% of that of a SiO2 MOSFET for an NFET and 96% for a PFET, were also obtained.

Thin films of ferroelectric Pb1−xCaxTiO3 (x=0.0–0.4) were formed on MgO, Pt/MgO, SrTiO3, and Pt/SrTiO3 substrates by rf magnetron sputtering. Characterization of the films by x-ray diffraction, x-ray precession, scanning electron microscopy, and electron probe microanalysis showed them to be epitaxially grown with their c-axis oriented perpendicular to the substrate. The decrease in the Curie temperature Tc and the increase in the pyroelectric coefficient dPs/dT with an increase in Ca doping were successfully explained by assuming that the Ca ions occupied Pb ion sites. Pyroelectric infrared detectors using Pb0.7Ca0.3TiO3 thin-film elements gave better performance than the detectors using PbTiO3 ceramic elements. The internal bias field EB and fixed polarization PB were observed to be a function of both the Ca content and temperature in ferroelectric hysteresis curves as well as in hysteresis curves of the dielectric constant as a function of the applied electric field. These phenomena were explained by the difference in thermal behavior between the sputtered films and the substrates at temperatures below Tc.