sThe embedded NVM technologies have been widely applied to logic-compatible processes [1] [2] for growing SOC demands, such as SMART CARD or NFC fields. A new NVM cell fully compatible with conventional logic process is introduced. Such a memory cell is fabricated by a typical 3.3V process, without any additional process steps or process change. Good characteristics are verified by using of both a single-cell testkey and a 1kbits test-array, demonstrating the feasibility of itself as an embedded NVM solution.Excellent endurance over 100K cycles is demonstrated and good retention result after 100K cycles have been presented as well. Cell structure and its operationThe proposed new cell is composed of four transistors and one capacitor, as in the Fig.1 to implement a single-poly floating-gate non-volatile memory device. The floating gate is shared by one n-MOSFET (M N1 ), one p-MOSFET (M P1 ) and one coupling capacitor (C 1 ); while the drain of M N1 connects to a read terminal, the drain of M P1 connects to a programming one. M N1 and M P1 are connected to their select-transistors, M N2 and M P2 , individually. As indicated in Fig. 1, the coupling capacitor, the two n-MOSFETs, and the two p-MOSFETs are enclosed with respective n-wells and p-well. Table 1 suggests the operation schemes for the new cell. The program and erase operations are performed on p-MOSFET by channel hot hole induced hot electron injection [3], and electron channel Fowler-Nordheim tunneling ejection, respectively. The read operation is performed on n-MOSFET by sensing read conduction current. Unlike conventional NVM devices, the proposed cell operation separates read path from program and erase path, in order to reduce the impact of program/erase operation induced degradation, such as Vth-window closure due to possible charge residues on gate dielectric layer. Therefore, an enhanced read current window is obtained for high reliability operation. Figure 2 shows the programming and erasing characteristics. By using of hot carrier injection at p-channel M P1 , the cell can be easily programmed with 6V in 100us; while a properly selected erasing bias applied (between 8 to 9V), the cell can be erased completely within 100ms. Fig. 3 shows the endurance trend by reading from n-channel M N1 . Vth-window is still good for read even after 10 6 program/erase cycles. Compared to read from p-channel M P1 , Vth-window by reading from M N1 has less degradation due to program/erase cycling stress as shown in Fig. 4. Fig. 5 and 6 illustrate the ID-VG characteristics of M N1 and M P1 before/after 10 6 program/erase cycles. Only Vth shift is observed for M N1 after program/erase cycle stress, which may come from the electron residue in floating-gate due to the degraded program/erase ability. For ID-VG curves of M P1 in Fig. 6, except for the electron residue, obvious sub-threshold swing degradation (20%) is observed, which indicates the operation-induced interface states change on M P1 after 10 6 program/erase cycling stress. Fig. 7 further depicts th...
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