In this paper, a novel scheme for detecting overflow in Residue Number System (RNS) is presented. A generalized scheme for RNS overflow detection is introduced, followed by a simplified Operands Examination Method for overflow detection for the moduli set . The proposed method detects overflow in RNS addition of two numbers without pre-computing their sum .Moreover, when compared with the best known similar state of the art designs, the proposed scheme requires lesser hardware, eruder htr izre heit epr and is faster.
This paper proposes a fast Mixed Radix Conversion based reverse converter for the recently proposed moduli set. It shows that the computation of multiplicative inverses could be eliminated from the conversion process and presents a low complexity and modulo operation free implementation. Theoretical analysis shows that the proposed scheme outperforms all state of the art equivalent converters in terms of both area cost and delay.
In this paper, we propose the new moduli set { − , , + } with an efficient reverse converter. Experiments were performed on our converter and the state of the art using Xilinx ISE 14.3 software to target a Spartan 3 FPGA board. The results from these experiments suggest that on the average, the proposed converter outperforms the state of the art converters for the moduli sets { −
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