System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for real-time signal processing due to their low, deterministic latency and high performance. We target our Audio Blade platform that contains an Intel Arria 10 SoC FPGA with floating-point capability and 1.5 TFLOPS performance. In order to target the Arria 10, the auditory nerve model [1, 2] needed to be ported to a hardware description language. We accomplished this by first porting the MATLAB/C model to Simulink, and then used MathWorks HDL Coder to generate VHDL code. Our hardware-accelerated model will allow researchers to edit model parameters in real-time from Linux software running on the embedded ARM CPUs and view the resulting nerve responses in real-time. The goal is to create a real-time platform running multiple auditory nerve models, allowing researchers to inject hearing impairments and then develop hearing aid strategies to compensate for these hearing deficits. We will discuss performance measures of the FPGA-based auditory nerve models, including latency measures and how many auditory nerve models can run simultaneously in the Arria 10 FPGA fabric. 1. Bruce et al., Hearing Res. 360, 40–54 (2018). 2. Zilany et al., JASA 126, 2390–2412 (2009).
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