The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters <= 200 mu m. An experimental investigation with uniform and double-side heat flux at Reynolds numbers <= 1,000 and heat transfer areas of 1 cm(2) was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mu m and fluid structure heights of 100-200 mu m. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm(2) heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from > 200 W/cm(2) at 1 cm(2) and > 50 mu m interconnect pitch to < 100 W/cm(2) at 4 cm(2). From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures
This paper shows how common embroidery can be used to integrate electronics into textile environment in a light and cost efficient way. A mechanism has been developed to embroider through flexible electronic modules using conductive yarn, thus creating an interconnection with other modules like sensors, batteries, textile keyboards, etc. Mold encapsulation has been found to improve the electrical contact and support the reliability of the whole system.
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the Spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation was performed for reliability assessment
Even though electroless Ni-P and Sn-Ag-Cu solders are widely used materials in flip-chip bumping technologies, interfacial reactions of the ternary Cu-NiSn system are not well understood. The growth of intermetallic compounds (IMCs) at the under bump metallization (UBM)/solder interface can affect solder-joint reliability, so analysis of IMC phases and understanding their growth kinetics are important. In this study, interfacial reactions between electroless Ni-P UBM and the 95.5Sn-4.0Ag-0.5Cu alloy were investigated, focusing on identification of IMC phases and IMC growth kinetics at various reflowing and aging temperatures and times. The stable ternary IMC initially formed at the interface after reflowing was the (Cu,Ni) 6 Sn 5 phase. However, during aging, the (Cu,Ni) 6 Sn 5 phase slowly changed into the quaternary IMC composed of Cu, Ni, Sn, and a small amount of Au. The Au atoms in the quaternary IMC originated from immersion Au plated on electroless Ni-P UBM. During further reflowing or aging, the (Ni,Cu) 3 Sn 4 IMC started forming because of the limited Cu content in the solder. Morphology, composition, and crystal structure of each IMC were identified using transmission electron microscopy (TEM) and scanning electron microscopy (SEM). Small amounts of Cu in the solder affect the types of IMC phases and the amount of the IMC. The activation energies of (Cu,Ni) 6 Sn 5 and (Ni,Cu) 3 Sn 4 IMCs were used to estimate the growth kinetics of IMCs. The growth of IMCs formed in aging was very slow and temperature-dependent compared to IMCs formed in reflow because of the higher activation energies of IMCs in aging. Comparing activation energies of each IMC, growth mechanism of IMCs at electroless Ni-P/ SnAgCu solder interface will be discussed.
I. IntroductionNetwork simulation has become more important for EMC analysis of conducted disturbances in power electronics over the last years. However, accurate models for the EMI frequency range from 10kHz up to 30MHz are rare and in most cases it is very difficult to obtain the appropriate model parameters. Furthermore, simulation time becomes more and more critical, if EMI phenomena of the whole power electronic system have to be investigated. Therefore, a good compromise between simulation time and model accuracy need to be found. Frequency domain simulations have been established for that task because of its high simulation speed even with complex models. On the other hand nonlinear behaviour of disturbance sources cannot be modeled in frequency domain [3]. Thus, time domain simulation is advantageous for certain simulation problems.Models for induction machines as a part of the EMI noise path have been presented by different authors. Weber has presented an exact model for frequency domain simulation [5] which is a further development of a proposed model by Zhong [6]. This model applies frequency dependent parameters and has high component count which leads to extensive simulation times. Thus, it is not useful for time domain simulations even when dependencies on the frequency are neglected. High frequency models of induction machines for time domain simulations have not been developed up to a comparable accuracy or they are not suitable to simulate both common mode (CM) and
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