This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.
This paper places a strong emphasis on the importance of applying the correct FA approach in physical sample preparation to identify hidden defects that can be easily removed during analysis. A combination of mechanical parallel polishing and chemical etching was used during the sample preparation after electrical fault isolation. Such a combination is both effective and efficient in identifying the single Via punch-through from a sea of Via in MIM structure as well as finding the thin layer of barrier bridging under the Al metal. It serves as a quick way to verify any suspect without time consuming FIB progressive cuts at the hotspot location which sometimes turns out to be an induced spot with a defect located at other site due to the circuitry connection. It would serve as a good reference to wafer fab that encountered such issues.
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