In this paper, a new memory cell along with a new peripheral circuit for SRAM in ultra fine advanced process technologies is presented. A unique feature of the proposed circuit technique is its circuit design concept to achieve the fully digital ratio-less operation. This enables memory cell design that is free from consideration of the Static Noise Margin (SNM). Furthermore, it enables SRAM function without the restriction of transistor parameter (W/L) settings in circuit design and the dependency on local process variation. To achieve these unique features, we propose (1) a ratio-less memory cell in which the flip/flop loop can be broken in write operation and a push-pull tri-state buffer for secure read operation and (2) the configuration of a static Column Retention Loop (CRL) to prevent loss of memory cell data in the write half-select state. Combining these two key circuit techniques, a new SRAM circuit that is free from design restriction of SNM was developed. A 0.18-µ µ µ µm 1024-bit MOSAIC SRAM TEG consisting of memory cells having all combinations of gate sizes of 10 transistors differing by two orders of magnitude was developed and tested to verify the proposed circuits.
MOSAIC SRAM Cell TEGs consisting of memory cells having all combinations of gate sizes of transistors differing by two orders of magnitude were developed with 0.18um CMOS process to verify the operation margins for SRAM circuits. The measured results show the operation of the ratio-less SRAM is completely independent of the size of transistors in the memory cell.
In this study, a ratioless full-complementary 12-transistor static random access memory (SRAM) was developed and measured to evaluate its operation under an ultra low supply voltage range. The ratioless SRAM design concept enables a memory cell design that is free from the consideration of the static noise margin (SNM). Furthermore, it enables a SRAM function without the restriction of transistor parameter (W/L) settings and the dependence on the variability of device characteristics. The test chips that include both conventional 6-transistor SRAM cells and the ratioless full-complementary 12-transistor SRAM cells were developed by a 180 nm CMOS process to compare their stable operations under an ultralow supply voltage condition. The measured results show that the ratioless full-complementary 12-transistor SRAM has superior immunity to device variability, and its inherent operating ability at the supply voltage of 0.22 V was experimentally confirmed.
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