Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vth's) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vth's are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski et al. was found to be the most suitable definition for predicting the distribution and the write yield.
It is still an open problem to elucidate the sealing merit of the embedded SRAM with the Low Operating Power (LOP) MOSFET's fabrication in 50, 70 and l o b CMOS technology node. Taking into account the realistic SRAM cell layout, we evaluate the parasitic capacitance of Bit Line (BL) as well as Word Line (WL) in each generation. By means of 3-Dimensional (3D) interconnect simulator (Raphael), we focus on the scaling merit through the comparison of the simulated SRAM BL delay in each CMOS technology node. In this paper, we propose two kinds of original interconnect structures which add some modifications to KRS, and clarify for the first rime that the o r i g i i interconnect structures guarantee the sealing merit of the SRAM cell fabricated with the LOP MOSFET's in 50 70 and IOOnm CMOS technology node.
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