This paper covers the motivations for and the advantagesof using an embedded DRAM compiler technology within a standard deep submicron logic process for System-on-a-Chip (SoC). We also discuss the bit cell design and the memory architecture, as well as the automation software and methodology used in the construction of the DRAM compilez Silicon resultsfrom the test chips are favorable. This approach makes economical and time-to-rnarket sense, therefore it can be a viable high-performance and area-efJicient option in the embedded DRAM technology.
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