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This paper proposes a frequency synthesizer using singleelectron transistor (SET)/MOS hybrid architectures for binary multiplier design. The main idea is to first convert the operands from their digital representation to frequency representation, and then perform multiplication in the frequency domain before converting the result back to the digital representation. The major merits of the proposed method include: 1) simplified implementation of binary multiplication and 2) high immunity against the background charges inherent in SET islands. Both circuit design and simulation are provided to show the effectiveness of the approach.Index Terms-Frequency synthesis, multiplier, SET/MOS hybrid architecture, single-electron transistor (SET).

Hybrid CMOS-SET architectures, which combine the merits of CMOS and single electron transistor (SET) devices, promise to be a practical implementation for nanometer scale circuit design. In this work, we propose the design of two typical arithmetic circuits, namely adder and multiplier, using hybrid CMOS-SET architectures. For full adders (FAs) design, we present three different implementations based on multiple-valued logic (MVL), phase modulation and frequency modulation. These FAs fully utilize SET's unique characteristic of Coulomb blockade oscillation and exhibit improved performance in terms of circuit area/complexity, power dissipation and temperature effect. The structure based on frequency modulation also possesses high immunity against background charges, and is extended to design of multiple-bit adder and multiplier.

Low temperature operation and background charge fluctuation are among critical limitations for practical single-electron-tunneling (or SET) based circuits. Particularly, background charges on the island of SET devices affect the phase of Coulomb blockade oscillation, and may eventually lead to incorrect circuit operation. In order to construct robust SET circuits, we explore new design methods based on feedback architectures and novel characteristics of SET devices. We first discuss the impact of a direct feedback on circuit performance against background charges. Then, we propose a self-adapted input-referred feedback structure which can drastically reduce the sensitivity of circuit behaviors to background charge fluctuations. An improved hybrid CMOS-SET ADC circuit is also presented as an example to take advantage of the proposed feedback architecture for robustness against random background charges.I.

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