Reversible logic is helpful in designing low power applications. Many reversible gates have been introduced in recent time for use in reversible computing. Those gates are used in the design of various circuits. In some works, decoders using reversible logic have been also proposed. This paper proposes three new reversible gates that can perform multiple logical operations alone. Using these gates, new circuits for 2-to-4 and 3-to-8 decoders are proposed followed by two new designs for general decoder. The performances of the proposed decoder circuits are studied in terms of hardware complexity, power, gate count, number of ancilla inputs and garbage outputs. Comparisons of these circuits with similar existing decoder circuits are also presented. The proposed circuits are found to have better performance characteristics particularly garbage output is least amongst available designs.
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