This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13 m CMOS technology. The analog baseband is compliant with several digital broadcasting system (DBS) standards, including DVB-S, DVB-S2, and ABS-S. The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz. The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step. The calibration includes automatic frequency tuning (AFT) and automatic DC offset calibration (DCOC) to achieve less than 6% cut-off frequency deviation and 3 mV residual output offset. The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively, while the input referred noise (IRN) is 17.4 nV/ p Hz. All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.
An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm 2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 mA under a supply of 1.2 V.
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