Abstract-The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that is based on Boolean Satisfiability. Furthermore, the principle limits of the original and the improved approach are shown. Then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. Experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude. I. INTRODUCTIONReversible logic has applications in low-power design, optical computing and especially in quantum computing. In the context of quantum computation it is known that some exponentially hard problems can be solved in polynomial time [1]. Necessarily all quantum computations are reversible. Therefore synthesis of reversible logic has become an intensively studied topic. The synthesis of reversible logic differs significantly from traditional irreversible logic. In a reversible network fan-out and feed-back are not allowed. Consequently a network for reversible logic consists of a cascade of reversible gates. The most frequently used gate type is the Toffoli gate [2] which will also be used in this paper. The idea of this gate is to invert one input line (the target line) if the product of a set of control lines evaluates to true.For the synthesis of reversible logic several approaches have been proposed. An approach that is based on enumeration and that uses network equivalences to rewrite a limited set of gates has been presented in [3]. Other synthesis procedures use heuristics like e.g. spectral techniques [4], positive polarity Reed-Muller expansions [5] or transformation based synthesis [6]. In [7] a method has been proposed that synthesizes the reversible function in a first step and then based on transformations (using so called templates) a realization with fewer gates is computed. An exact synthesis method based on reachability analysis is described in [8]. However, this procedure is geared towards quantum gates, not Toffoli gates. Recently, in [9] the first exact synthesis approach for reversible logic using generalized Toffoli gates has been presented. This approach uses Boolean Satisfiability (SAT) during the synthesis process. Since the synthesis problem is transformed to the Boolean level complexity problems occur.The contribution of this paper is twofold. First, we lift the encoding of the synthesis problem to a higher level. Based on this formulation, the SAT solver used in [9] is replaced by a Satisfiability Modulo Theories (SMT) solver. As shown by the experiments this already leads to a significant speed-up of the synthesis algorithm. Second, after a detailed analysis of the principle limits of these synthesis procedures we propose a compl...
Abstract-Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible logic synthesis, testing, and verification have been investigated, debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an erroneous circuit that explain the observed incorrect behavior.In this paper we propose the first approach for automatic debugging of reversible Toffoli networks. Our method uses a formulation for the debugging problem based on Boolean satisfiability. We show the differences to classical (irreversible) debugging and present theoretical results. These are used to speed-up the debugging approach as well as to improve the resulting quality. Our method is able to find and to correct single errors automatically.
Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are several techniques that can check if a set of formal properties forms a complete specification of a design. But, in contrast to simulationbased methods, like random testing, formal verification requires a detailed knowledge of the design implementation. Finding the correct set of properties is a tedious and time consuming process. In this paper, two techniques are presented that provide automatic support for writing properties in a quality-driven BMC flow. The first technique can be used to analyze properties in order to remove redundant assumptions and to separate different scenarios. The second technique -inverse property checkingautomatically generates valid properties for a given expected behavior. The techniques are integrated with a coverage check for BMC. Using the presented techniques, the number of iterations to obtain full coverage can be reduced, saving time and effort.
In the last years synthesis of reversible logic functions has emerged as an important research area. Other fields such as low-power design, optical computing and quantum computing benefit directly from achieved improvements. Recently, several approaches for exact synthesis of Toffoli networks have been proposed. They all use Boolean satisfiability to solve the underlying synthesis problem. In this paper a new exact synthesis approach based on Quantified Boolean Formula (QBF) satisfiability -a generalization of Boolean satisfiability -is presented. Besides the application of QBF solvers, we propose Binary Decision Diagrams to solve the quantified problem formulation. This allows to easily support different gate libraries during synthesis. In addition, all minimal networks are found in a single step and the best one with respect to quantum costs can be chosen. Experimental results confirm that the new technique is faster than the best previously known approach and leads to cheaper realizations in terms of quantum costs.
It was the aim of this study to elucidate whether intraportally transplanted pancreatic islets were reinnervated after transplantation and whether the secretion of insulin from pancreatic islets might be modulated by the vegetative innervation of recipient livers. Two weeks after intraportal transplantation of 2000 neonatal pancreatic islets recipient rats completely recovered from streptozotocin-induced diabetes. Predominantly catecholaminergic, but also cholinergic nerve fibers were detected in islet cell complexes between beta-cells. Corresponding electron micrographs showed beta-cells in close contact with axons of nonmyelinated nerve fibers. Perfusion studies with livers of recipient rats revealed that the inhibition by hepatic sympathetic nerves of insulin secretion was mediated via alpha 2-receptors as in normal pancreatic islets.
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