A great number of spatially distributed transceiver chips within multiple-input multiple-output radar systems make the reference signal synthesis as well as its distribution to an emerging topic. Therefore, we introduce a synthesizer based on the concept of fractional-N division which is able to provide a linear frequency ramp around 200 MHz. Furthermore, an ultra wideband phase-locked loop (PLL) is presented using this synthesizer and featuring a bandwidth of 22 GHz centred around 85 GHz. For stabilizing the PLL over the complete bandwidth a passive auxiliary circuit has been developed. The system achieves a phase noise below -78 dBc/Hz at 10kHz offset over its complete bandwidth
A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fractional-N synthesizers is presented. The division factor can be set to all integer values between 12 and 259 and is applied by an 8 bit parallel interface for fast modulation. The remarkably high input frequency in combination with the programmability is achieved by a dual-modulus concept and differential emitter-coupled logic with a consequent merging of logic gates into flip-flops. Among this, a reset function has been implemented to synchronize multiple synthesizers. The frequency divider has been realized in a SiGe BiCMOS technology (fr/fmax=250/360 GHz). The divider works at a supply voltage of 3.3 V with a power consumption of less than 390 mW
The performance of frequency synthesizers with respect to bandwidth and phase noise limits the overall performance of high precision FMCW radar systems. An essential challenge of fractional-N ramp synthesizers is to combine high reference frequency and low division ratio in the loop to minimize phase noise. For an 80GHz radar system with ultra high bandwidth of 24.5 GHz we meet this challenge with a programmable frequency divider with unrivaled high input frequency. These building blocks have been implemented on a single SiGe integrated circuit. The developed phase-locked loop (PLL) includes a reverse phase downconversion mixer driven by a fixed frequency PLL to attain constant loop gain. The phase noise of the fixed frequency PLL has been measured to be -104 dBc/Hz at 20kHz offset from the center frequency of 48 GHz, which enables a phase noise of the 80GHz radar output of -93 dBc/Hz at 20 kHz offset frequency
A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. The measured input frequency range is from DC to 57 GHz for division factors in the entire integer range between 12 and 259 as well as 8 and 9. The frequency divider is based on a dual-modulus concept and has been realized in a SiGe bipolar technology (fT/fmax=170/250 GHz). The exceedingly high maximum input frequency has been reached by using emitter-coupled differential circuit technique with a consequent merging of logic operations and D flip-flops. The divider is designed for low power consumption of less than 300mW at a supply voltage of 3.3V. For the intended use in a fractional-N frequency synthesizer for the millimeter wave range, the division ratio is programmable via an 8 bit parallel interface to enable fast modulation of the division factor
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