3D chip stacking are the solution for achieving more transistors on microchips. Through Si via (TSV) is the key for 2.5D and 3D technology. In this paper, a novel integrated descum technique are evaluated to improve both etch and litho process margin and TSV profile. Using a proper and optimized de-scum methodology for TSV etch we demonstrated a defect free TSV profile without any significant process integration impact and also throughput loss.
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