To fundamentally solve the bottleneck of Von Neumann's computing architecture, a neuromorphic thin-film transistor (NTFT) employing Pb(Zr, Ti)O3 (PZT) was investigated. The indium gallium zinc oxide (IGZO) channel back gate TFT structure was chosen to solve the diffusion of atoms that form a channel layer during the annealing process for crystallization of PZT. A post-deposition process with IGZO after annealing PZT and using an oxide-based material as a channel structure can minimize the diffusion phenomenon of junction materials and oxygen together, which leads to a high and reliable performance of the NTFT. The basic operations of synapses short-term memory (STM) and long-term memory (LTM) were also analyzed to confirm the application of a neuromorphic device. The high dielectric constant and polarization properties of Pb(Zr, Ti)O3 (PZT) allow the power consumption of spike signals used in spike dependent plasticity change to be reduced to 10 pJ. Moreover, a wide dynamic range of Gmax / Gmin ≅ 1000 was obtained, and the channel conductance was maintained over 40000 seconds. The optimized pulse achieved multi-level states (>32), which made the learning process efficient. This study verified that the PZT-TFT structure has a high potential and merits for neuromorphic devices.
The vertical thin film transistor (VTFT) has several advantages over the planar thin film transistor, such as a high current density and low operating voltage, because of the structural specificity. However, it is difficult to realize transistor operation in a VTFT because of the structural limitation that the gate field is blocked. As a solution, the conductivity modulation of a graphene electrode is studied with a micro‐hole structure as a gate field transfer electrode. The micro‐hole array pattern in the graphene allows better penetration of the gate field to junction and the work function to be modulated. Moreover, the patterning induces a doping effect on the graphene which results in a high barrier at the p–n junction and improves the conductivity in the device operation. The optimum performance is shown at 5 µm hole size and 30% hole ratio by analyzing the hole size and the area ratio. The proposed structure shows about 20 times higher on‐current than a planar transistor with a same active area. Compared to a VTFT using simple graphene working function modulation, the proposed structure has an on‐state current that is ten times higher and off‐state current that is reduced 50%, and therefore has an improved on–off ratio.
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