groups have recently and independently demonstrated that, by applying an electric fi eld across a pristine fi lm of 3D hybrid perovskites of different chemical composition, a self-sustained fi eld is induced in the semiconductor as a consequence of ion migration toward the electrode regions. [10][11][12][13] The formation of a self-sustained internal fi eld upon device polarization is also in good agreement with the observations reported by Tan et al. when testing perovskite-based light emitting diodes. [ 14 ] This concept has also been the base of the explanation proposed by Tress et al. for the rate-dependent hysteresis seen in current-voltage scans of solar cells. [ 15 ] So far reports suggest that transient electrical characteristics are due to a polarization response of the perovskite active layer that results in changes in the photocurrent extraction effi ciency of the device. [ 11,15 ] However, it must be noted that a variety of dynamics have been reported, which differ in magnitude and time scale, depending both on the specifi c device architecture and, in particular, on the adopted charge extraction layer. [ 7,9 ] This indicates that contact interfaces have a considerable effect on transients in perovskite based devices.In this Communication we investigate the role played by charge extracting layers on the slow transient behavior of CH 3 NH 3 PbI 3 perovskite based solar cells. Such transients, which typically affect both short-circuit currents and open circuit voltage of hysteretic devices, are found to notably modify the open circuit voltage also in the very fi rst J -V scans of so-called "hysteresis-free" devices integrating a phenyl-C61-butyric acid methyl ester (PCBM) charge extraction layer. Here a preconditioning of the device, i.e., a repetition of J -V scans, is needed to achieve completely stable J -V characteristics under illumination. In particular, we fi nd that under device operation, iodide ions migrate to the electron extracting layer. We fi rst show that the use of an organic extraction layer such as PCBM, albeit not hampering ions motion, evidently improves charge extraction with respect to interfaces involving compact TiO 2 , in agreement with what is suggested in other seminal investigations, [ 16,17 ] and makes the short-circuit current density virtually insensitive to the transient phenomena related to ions migration. Moreover, while self-doping of the perovskite fi lm close to the contact has been generally put forward in the study of transient phenomena, [ 12,13 ] here we show that ions can specifi cally interact with the organic electron extracting layer, inducing electronic doping and that such I − /PCBM interaction is at the origin of the preconditioning requirement for stabilizing the device and for improving its open circuit voltage with respect to the fi rst scan.Solution-processable hybrid perovskite semiconductors have risen to the forefront of photovoltaics research, offering the potential to combine low-cost fabrication with high-powerconversion effi ciency. Originally u...

Current voltage measurement of three different PEDOT:PSS printed lines Figure S1. Current-voltage characteristics of all three different PEDOT:PSS printed lines. Inset (a) optical micrograph and (b) thickness profiles of the printed lines.

The increasing diffusion of portable and wearable technologies results in a growing interest in electronic devices having features such as flexibility, lightness-in-weight, transparency and wireless operation. Organic electronics was proposed as a potential candidate to fulfill such needs, in particular targeting pervasive Radio-Frequency (RF) applications. Still, limitations in terms of device performances at RF, particularly severe when large-area and scalable fabrication techniques are employed, have largely precluded the achievement of such an appealing scenario. In this work, the rectification of an electromagnetic wave at 13.56 MHz with a fully inkjet printed polymer diode is demonstrated. The rectifier, a key enabling component of future pervasive wireless systems, is fabricated through scalable large-area methods on plastic. To provide a proof-of-principle demonstration of its future applicability, its adoption in powering a printed integrated polymer circuit is presented. The possibility of harvesting electrical power from RF waves and delivering it to a cheap flexible substrate through a simple printed circuitry paves the way to a plethora of appealing distributed electronic applications. Main text:The rising demand for automatic identification procedures has resulted in an increasing request of portable and pervasive devices, such Radio-Frequency IDentification (RFID) tags, which could be used, for example, to identify everyday objects through electronic serialization codes.In general, RFID devices can be classified depending on the frequency at which they operate.Low-frequency (LF) RFID tags work at 120-145 kHz (LF), high-frequency (HF) tags at 13.56 MHz (HF), and ultra high-frequency (UHF) tags operate at frequencies higher than 860 MHz. [1] Another typical classification of RFID devices is related to the presence or not of a power supply or battery. Active RFID tags contain their own power source giving them the ability to broadcast with a read range of up to 100 meters (far-field communication protocols), so they typically operate in the UHF regime. Passive RFIDs do not have any power supply: all the power required for operating the tag is generated by converting the alternating-current (AC) RF signal received from an antenna into a direct-current (DC) power supply. Thus, the RFID tag usually contains a low resistance antenna and a high-frequency rectifier for AC to DC conversion.Passive RFID tags usually can be read from few cm for proximity readers (near-field communication protocol) and up to 1 m for vicinity readers. Choice of the specific RFID device depends on the target application and it is typically a trade-off among required reading distance, costs and technological constraints. Cost-effective passive tags are more suited for high volume products of limited intrinsic value and the HF range is preferable where bulky coils, such as those required for LF, are not an option, and tag flexibility and ease of

Using a combination of nanoimprint lithography, gate-source/drain self-alignment, and gravure and inkjet printing, we fabricate organic field-effect transistors on flexible plastic substrates with gate-source and gate-drain electrode overlap capacitances of COL < 1 pF, equivalent to channel-width normalised capacitances of C*OL = 0.15–0.23 pF mm−1. We compare photopatterned and nanoimprint lithography patterned channels of L ≈ 3.8 μm and L ≈ 800 nm, respectively. The reduction in L was found on average to result in order of magnitude greater switching frequencies. Gravure printing the dielectric (versus photo-patterning) was found to yield an order of magnitude lower overlap capacitance C*OL = 0.03 pF mm−1, at the expense of greater processing variation. Inkjet printed p- and n-type polymeric organic semiconductors were used to fabricate organic-field effect transistors with a peak cutoff frequencies of fS = 9.0 ± 0.3 MHz at VGS = 30 V, and transition frequencies of fT = 3.3 ± 0.2 MHz at VGS = 30 V.

Perovskite‐based solar cells manifest often an electrical instability in terms of current‐voltage hysteresis. In article number 1501453, Mario Caironi, Annamaria Petrozza and co‐workers demonstrate how fullerene based electron extracting layers stabilize the short‐circuit photocurrent from the very first J–V scan, thanks to efficient electron extraction, while preconditioning cycles are needed to stabilize the open‐circuit voltage owing to interaction between migrating iodide ions and the charge extraction layer, which result in the doping of the fullerene.

photo detectors. [ 10 ] Similarly gravure printing has been used to fabricate circuits such as: complementary ring oscillators, [ 11 ] logic gates, [ 12 ] unipolar fl ip-fl ops and half-adders. [ 13,14 ] Although previous reports have combined gravure and inkjet printing to fabricate p-type organic fi eld-effect transistors (OFETs), [ 15 ] there is a lack of direct comparative studies of the impact of each process on the electrical performance of devices. Here, we explore gravure versus inkjet printing of semiconductors, gravure printing versus photolithographic patterning of the OFET dielectric, and long-channel (>1 µm) versus short channel (<1 µm) OFETs.Gravure printing enables very large-area, fast, roll-to-roll manufacturing, limited by the expense and time cost of fabricating clichés (printing plates). [ 16,17 ] Inkjet printing enables a computer-designed circuit to be printed readily and easily, limited by the relative throughput and speed of printing. [ 2 ] However, the resolution of both technologies is still restricted to the micrometer scale and larger by the challenge of reliably transferring inks onto a substrate without spreading or dewetting, while still maintaining electrical performance. While recent approaches are improving upon this limit, for example, the work of Kang et al. on gravure printed sub-5 µm gate electrodes, [ 18 ] or that of Sekitani et al. on 2 µm inkjet printed electrodes, [ 19 ] the options for patterning sub-micrometer electrode geometries are limited.We have previously demonstrated how ultraviolet nanoimprint lithography (UV-NIL) is a viable method for patterning sub-micrometer channel length OFETs on plastic. [ 20 ] Our approach also uses self-aligned lithography to minimize the overlap between the gate-source and gate-drain electrodes, reducing parasitic overlap capacitances that reduce the switching speed of OFETs. [ 21,22 ] Self-alignment yields other benefi ts such as overcoming equipment alignment tolerances, reducing leakage currents, and is compatible with more complex circuitry such as self-aligned unipolar ring oscillators. [ 23 ] In this work, we have used bottom-gate bottom-contact architectures, to avoid exposing the semiconductor to both the ultraviolet light and processing chemicals used for self-alignment. In addition to self-alignment, here we extend the fabrication approach further by incorporating gravure printed dielectrics and semiconductors, as well as inkjet printed semiconductors. We demonstrate both p-and n-type devices patterned side-by-side on the same substrate along with complementary inverters and logic gates. Figure 1 illustrates the materials and architectures used in this work. Aluminum OFET gates were patterned either photolithographically (PL) or via UV-NIL. A cross-linkable proprietary dielectric (GSID 938109-1, BASF) [ 24,25 ] was either PL patterned or gravure printed. Self-aligned gold electrodes were patterned Organic electronics is a maturing fi eld, [ 1 ] replete with a large variety of devices and fabrication technologies. [ 2 ] Often...

cost-effective manufacturing techniques. Organic materials can be processed from solution, mostly by means of printing and coating techniques, which are lowtemperature processes, enable mass production, and minimize the by-products. [4] Being these manufacturing techniques compatible with flexible, plastic and other low-cost substrates, there is a clear potential for the integration of additional electronic functionalities into mass-produced, consumer products. [5][6][7] In order to meet very stringent costs constraints, which do not allow integration of conventional electronic chips, all-organic circuits fabricated by means of scalable techniques are one of the best options.One of the main limitations hindering the adoption of all-organic printed circuits in real applications is related to their operating voltage. [8] In order to grant their portability and easy integration, these circuits need in fact to be powered by thin film batteries [9,10] and/or energy harvesters, such as plastic solar cells, [11,12] thus requiring maximum operation voltages of a few volts and low power consumption, while keeping reasonably high values of accumulated charge density and of current flowing into the circuits. Efficient low voltage operation can be achieved by acting on the capacitance of the dielectric layer, which should be as high as possible and at the same time guarantee optimal charge accumulation and transport at the semiconductor-dielectric interface of both holes and electrons, in order to enable complementary architectures to drastically reduce power consumption. [13,14] Many efforts have been recently devoted to the development of suitable polymer materials for gate dielectric applications, aiming at the achievement of the highest possible gate capacitance. [13] Two main strategies may be followed, either increasing the dielectric constant of the employed material or decreasing its thickness. The integration of high-k materials as dielectrics is not straightforward, as the energetic disorder at the interface might interfere with charge transport inside the semiconductor layer. [15,16] Multilayer structures combining low-k and high-k materials have been therefore introduced. [17,18] However, high-k materials typically show dielectric relaxations occurring at low frequency, [19,20] possibly limiting the maximum operation frequency of OFETs. Such limit is particularly severe in electrolyte gated transistors, [21] where huge capacitances are achieved at the expense of the switching speed because of ions motion, even in recent solidstate electrolytes. [22] To avoid such limitations, an obvious In the path toward the integration of organic field-effect transistors (OFETs) and logic circuits into low-cost and mass produced consumer products, all-organic devices based on printed semiconductors are one of the best options to meet stringent cost requirements. Within this framework, it is still challenging to achieve low voltage operation, as required by the use of thin film batteries and energy harvesters, for which a high c...

Ambipolar semiconducting polymers, characterized by both high electron (μ e) and hole (μ h) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two condction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μ h = 0.29 cm2/V s and μ e = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μ e = 0.12 cm2/V s and μ h = 8 × 10 -4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic. © 2014 AIP Publishing LLC