Abstract-Nowadays, the microelectronics market is characterized by an increasing complexity and integration, in particular in the field of application specific integrated circuits (ASICs) not only for digital but also for mixed-signal designs. The lack of a well defined methodology for analog synthesis, similar to the digital field means a serious drawback for analog and mixed signal design development. In this sense, the arise of VHDL-AMS is a recent evolution which promises to link analog design automation tasks into a coherent framework, in a similar fashion that digital design. In this paper, a tool to perform automated synthesis of analog systems, described in VHDL-AMS, into analog programmable devices is presented. The tool is focused to synthesise filters, wave-shaping circuits, amplifiers and in general most circuits supported by programmable technology. It is demonstrated with a practical example of a analog system composed by two filters and two controllable gain stages.
This work presents a new analog architecture to perform image convolution for deep learning purposes in CMOS imagers in the analog domain. The architecture is focused to reduce both power dissipation and data transfer between memory and the analog operators. It uses mixed signal multiply and add operators arranged following a row-parallel architecture in order to be fully scalable for different CMOS imager sizes. The multiplier circuit used is based on a current mode architecture to multiply the value of analog inputs by the digital stored weights and produce current mode outputs which are then added to obtain the convolution result. A digital control circuit manages the pixel readout and the multiply and add operations. The architecture is demonstrated performing 3x3 convolutions on 64x64 images with a padding equal to 1. Convolution weights are locally stored as 4bit digital values. The circuit has been synthesized in 110 nm CMOS technology. For this configuration, the simulation results show that the circuit is able to perform a whole convolution in 32 us and achieve an efficiency of 2.13 TOPS/W. These results can be extrapolated to larger CMOS imagers and different mask sizes.
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