An improved technique for the design of an unbalanced analog reflection-type on-chip vector modulator is presented. At microwave frequencies, voltage-controlled high-electron-mobility transistor (HEMT) like pseudomorphic HEMT (pHEMT) is often chosen as the variable termination in vector modulator. However, the parasitic elements of the transistor introduce amplitude and phase errors, which will degrade the overall performance of the vector modulator. Based on the establishment of pHEMT scalable parasitic model and characterization of bond-wire interconnection, we propose a method and a corresponding design procedure that mitigate the parasitic effects of pHEMT and achieve optimum performance of the vector modulator. The influences of Lange coupler characteristic impedance and compensation inductance on the vector modulator are analyzed first. Then, a method to determine the optimal values of characteristic impedance and compensation inductance is given, which relieves parasitic effects and obtains symmetric constellation. In our proposed design, the compensation inductance is realized through bond-wire inductance, eliminating the requirement of the on-chip inductor. To validate the design concept, a vector modulator module, composed of power divider, Lange coupler, and variable termination, is designed with each part fabricated separately using 0.15-µm GaAs pHEMT process and assembled on Rogers 5880 substrate with 10-mil-thick printed circuit board. The assembled vector modulator is characterized using an automatic test setup. The measured symmetric constellation is in good agreement with the simulation result, which indicates the effectiveness of the proposed design method and assembly process. INDEX TERMS Cold pHEMT, bond-wire, microwave integrated circuit (MMIC), parasitic elements, vector modulator.
This paper discusses motivation and design of an offset mixer and investigates its optimum placement in loopback test setup for on-chip RF test. Based on this study, design and implementation of an offset mixer for on-chip RF testing of radio front ends is presented. The offset mixer is passive in nature reducing silicon area and power overheads. Mixer is implemented and the design aims for dual band operation i.e. Bluetooth & WLAN standards and high linearity. Post layout results indicate that the mixer has excellent noise figure of 5dB, low conversion loss of less than 5dB as well as high IP3 of 12.5 dBm. Proposed passive offset mixer with almost zero dc power consumption and minimal silicon area makes it best suitable for on chip RF test. Pre & post-layout simulation results obtained with Cadence Spectre RF are presented.
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