We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic
(PTL) structure that mixes conventional PTL structure with static logic gates can
achieve better performance and lower power consumption compared to conventional
PTL structure. The goal is to use the static gates to perform both logic functions as well
as buffering. Our experimental results demonstrate that the proposed mixed PTL
structure beats pure static structure and conventional PTL in 9 out of 15 test cases for
either delay or power consumption or both in a 0.25 μm CMOS process. The average
delay, power consumption, and power-delay product of the proposed structure for 15
test cases are 10% to 20% better of than the pure static implementations and up to 50%
better than the conventional PTL implementations.
We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates with different body bias circuits in two different 0.13 µm SOI CMOS technologies. The experimental results show that the proposed SOI PTL gate using the body bias controlled technique is superior in terms of performance and power consumption than other DTMOS PTL gates.
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