A 434/868 MHz FSK/OOK transmitter with integrated PLL is reported. Direct digital modulation of a fully integrated ∑-∆ fractional-N PLL frequency synthesizer is used to ensure fine frequency resolution and low phase noise. A wideband VCO together with an Adaptive Frequency Calibration (AFC) is used to cover the desired bands. A differential-to-single output programmable power amplifier is integrated to make the chip low cost and low power. The measurement results show that the phase noise are -76dBc/Hz and -131dBc/Hz at 10-kHz offset and 3-MHz offset with carrier centered at 868 MHz, respectively. The peak output power of the transmitter is 3.5dBm on 50-Ω load and the measured adjacent channel power ratio (ACPR) for 100 kHz channel is less than -50-dBc. The chip is fabricated with 0.35-µm RF CMOS process. The 2-mm 2 transmitter IC including PLL and power amplifier (PA) consumes 87.6mW at 3V voltage supply.I.
A 2.4G single-chip radio-frequency (RF) transceiver front-end for IEEE 802.11b is integrated in 0.18 ,um CMOS technology. The direct conversion architecture is adopted for both transmitter & receiver to minimize the on-chip and off-chip components required, which ensures low cost and low power consumption. The VCO oscillates at two times the carrier frequency to minimize PA pulling effect, which also facilitates the generation of quadrature LOs by using a divide-by-two circuit. It is also promising that further integration of multi-mode transceiver can be facilitated because this architecture maximizes reuse of building blocks in transmitter, receiver and PLL. Primary test results show that the transmit peak error vector magnitude (peak EVM) is less than 16% (rms value about 8.6%) with the spectrum mask requirements met and show that at 4.4GHz, PLL phase noise is about -119dBc/Hz at 3MHz offset.
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