Two lightweight block cipher families, Simon and Speck, have been proposed by researchers from the NSA recently. In this paper, we introduce Simeck, a new family of lightweight block ciphers that combines the good design components from both Simon and Speck, in order to devise even more compact and efficient block ciphers. For Simeck32/64, we can achieve 505 GEs (before the Place and Route phase) and 549 GEs (after the Place and Route phase), with the power consumption of 0.417 µW in CMOS 130nm ASIC, and 454 GEs (before the Place and Route phase) and 488 GEs (after the Place and Route phase), with the power consumption of 1.292 µW in CMOS 65nm ASIC. Furthermore, all of the instances of Simeck are smaller than the ones of hardware-optimized cipher Simon in terms of area and power consumption in both CMOS 130nm and CMOS 65nm techniques. In addition, we also give the security evaluation of Simeck with respect to many traditional cryptanalysis methods, including differential attacks, linear attacks, impossible differential attacks, meet-in-the-middle attacks, and slide attacks. Overall, all of the instances of Simeck can satisfy the area, power, and throughput requirements in passive RFID tags.

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High-speed mobility and heavy-load traffic in mobile Ad hoc networks (MANET) may result in frequent topology changes and packet loss. To guarantee packet delivery, a novel stable backup routing (SBR) scheme is put forward in this paper, which consists of the establishment of backup routes and route maintenance. In SBR, backup routes are set up by overhearing MAC signals, and the bit error rate is considered in path selection for improving stability. To repair broken links effectively and reasonably, qualified backup routes are classified into three categories with different priorities, based on which the relevant nodes decide how to reconstruct the forwarding path. Extensive simulations demonstrate that our proposed method outperforms other comparable backup routing mechanisms in terms of packet delivery ratio, average delay and control overhead.

WG-8 is a lightweight instance of the Welch-Gong (WG) stream cipher family, targeting for resource-constrained devices like RFID tags, smart cards, and wireless sensor nodes. Recent work has demonstrated the advantages of tower field constructions for finite field arithmetic in the AES and WG-16 ciphers. In this paper we explore three different tower field constructions for WG-8. The first tower field is tailored to FPGA cells. The second tower field uses a Type-I optimal normal basis. The third tower field exploits algebraic properties of the WG permutation and trace functions. All of the methods use a parallel LFSR to provide data rates from one to eleven bits per clock cycle. Among the three tower fields, the Type-I ONB construction offers the best trade-off in area, speed, and power consumption. However, a plain monolithic look-up table implementation with 256 entries is smaller and faster than the tower field constructions. Our analysis of the tower field options and comparisons to each other and to the monolithic look-up table will provide lessons for future work in exploring novel tower field constructions for WG and other ciphers.

Fruit-80, which emerged as an ultra-lightweight stream cipher with 80-bit secret key, is oriented toward resource constrained devices in the Internet of Things. In this paper, we propose area and speed optimization architectures of Fruit-80 on FPGAs. Our implementations include both serial and parallel structure and optimize area, power, speed and throughput respectively. The area optimization architecture aims to achieve the most suitable ratio of look-up-tables and flip-flops to fully utilize the reconfigurable unit. It also reuses NFSR and LFSR feedback functions to save resources for high throughput. The speed optimization architecture adopts a hybrid approach for parallelization and reduces the latency of long data paths by pre-generating primary feedback and inserting flip-flops. Besides, we recommend using the round key function to optimize serial or parallel implementations for Fruit-80 and using indexing and shifting methods for different throughput. In conclusion, our results show that the area optimization architecture occupies up to 35 slices on Xilinx Spartan-3 FPGA and 18 slices on Xilinx 7 series FPGA, smaller than that of Grain and other common stream ciphers. The optimal throughput/area ratio of the speed optimization architecture is 7.74 Mbps/ slice, better than that of Grain v1, which is 5.98 Mbps/ slice. The serial implementation of Fruit-80 with round key function occupies only 75 slices on Spartan-3 FPGA. To the best of our knowledge, the result sets a new record of the minimum area in lightweight cipher implementation on FPGA.