Scalability and performance of current flash memories can be improved substantially by replacing the floating poly-Si gate by a layer of Si dots. This multi-dot layer can be fabricated CMOS-compatibly in very thin gate oxide by ion beam synthesis (IBS). Here, we present both experimental and theoretical studies on IBS of multidot layers consisting of Si nanocrystals (NCs). The NCs are produced by ultra low energy Si + ion implantation, which causes a high Si supersaturation in the shallow implantation region. During post-implantation annealing, this supersaturation leads to phase separation of the excess Si from the SiO 2 . Till now, the study of this phase separation process suffered from the weak Z contrast between Si and SiO 2 in Transmission Electron Microscopy (TEM). Here, this imaging problem is resolved by mapping Si plasmon losses with a Scanning Transmission Electron Microscopy equipped with a parallel Electron Energy Loss Spectroscopy system (PEELS-STEM). Additionally, kinetic lattice Monte Carlo simulations of Si phase separation have been performed and compared with the experimental Si plasmon maps. It has been predicted theoretically that the morphology of the multidot Si floating-gate changes with increasing ion fluence from isolated, spherical NCs to percolated spinodal Si pattern. These patterns agree remarkably with PEELS-STEM images. However, the predicted fluence for spinodal patterns is lower than the experimental one. Because oxidants of the ambient atmosphere penetrate into the as-implanted SiO 2 , a substantial fraction of the implanted Si might be lost due to oxidation.Metal-Oxide-Silicon Field-Effect-Transistors (MOSFETs) with an electrically isolated ("floating") gate layer embedded in the gate oxide are currently used as flash memories. The replacement of this floating-gate by a layer of discrete Si nanocrystals (NCs) [1] improves the performance of flash memories substantially [2]. The reduced probability for a complete discharging of the multi-dot floating-gate by oxide defects allows thinner tunnel oxides. In turn, the floatinggate will be charged/discharged by quantum mechanical direct electron tunneling (instead of defect-generating FowlerNordheim tunneling). The memory operation voltage can be reduced and scalability is improved. Using ion beam synthesis, the multi-dot floating-gate can be fabricated along with standard CMOS processing [3]. Si + ions are implanted at ultra low energies into the gate oxide, causing there a high Si supersaturation. During post-implantation annealing, this Si supersaturation leads to phase separation of elemental Si from SiO 2 [4]. Imaging this phase separation process is difficult. Till now, Transmission Electron Microscopy (TEM) has suffered from weak Z contrast between Si and SiO 2 phases. Recently, this problem was partially overcome by Fresnel imaging using under-focused bright field conditions [5]. Thus, the distance of the layer of phase separated Si from the transistor channel could be determined [6,7]. However, this technique fails to resol...
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