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ABSTRACT (Maximum 200 words)This paper presents a highly-integrated, high-precision FFT architecture. A 1.2 jm CMOS implementation of this architecture has yielded a 32-bit, 64K-point FFT that operates at a continuous 4-million-samples-per-second data rate. All FFT support functions, including coefficient generation and memory interfacing, are included on-chip.
Wireless environments present significant challenges to the operation of many of today's networking protocols. This paper explores how the wireless problem domain can be represented as a design space of a few independent variables, namely: reliability, latency, and bandwidth. These variables can be chosen in such a way as to match the wireless environment to the needs of the data being communicated. We select a single type of data, TCP bulk data transfer, and illustrate how the operating point in the design space is chosen. A simulation is presented which demonstrates that by matching the operating point in the wireless problem domain design space to the expectations of the data, much better pedormance is realized.
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