Functional testing of HDL spec$cations is one of the most promising approaches for the verijication of the f i n etionalities of a design before synthesis. The contribution of this work is the development of a test generation algorithm targeting a new coverage metric (called bit-coverage) that provides full statement coverage, branch coverage, condition coverage and partial path coverage for behaviorally sequential models. The behavioral test sequences can be also the only way to evaluate testability of VHDL model for which a gate-level representation is not available (e.g third-party cores), since the behavioral error model is characterized also by a high correlation with the RT and gate-level stuck-at fault model. Moreovec the preciseness of the proposed coverage metric makes the identijied test sequences more effective in identifiing design errors, than other test patterns developed by following standard coverage metrics.
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