The actin cytoskeleton usually lies beneath the plasma membrane. When the membrane-associated actin cytoskeleton is transiently disrupted or the intracellular pressure is increased, the plasma membrane detaches from the cortex and protrudes. Such protruded membrane regions are called blebs. However, the molecular mechanisms underlying membrane blebbing are poorly understood. This study revealed that epidermal growth factor receptor kinase substrate 8 (Eps8) and ezrin are important regulators of rapid actin reassembly for the initiation and retraction of protruded blebs. Livecell imaging of membrane blebbing revealed that local reassembly of actin filaments occurred at Eps8-and activated ezrin-positive foci of membrane blebs. Furthermore, we found that a RhoA-ROCKRnd3 feedback loop determined the local reassembly sites of the actin cortex during membrane blebbing.membrane bleb | Rnd3 | Eps8 | actin cortex | cell migration

Multilamellar vesicles (300-350 nm) were infused into the rat femoral vein at the rate of 4, 40 and 400 nmol phosphatidycholine min-1 for 6 h using [3H]inulin as an aqueous marker. The time courses of blood concentration of vesicles, normalized for infusion rate, were not superimposable, showing the non-linearity of liposome disposition in the blood circulation. These time courses of blood concentration were well fitted by a single Michaelis-Menten equation. On the other hand, the time courses of tissue content could not be so accommodated. Additionally, the observed relationship between the uptake of liposomes by the liver and their clearance from it and other organs differed essentially from a simulation based on Michaelis-Menten type saturable kinetics. Therefore, it is suggested that there is a time-dependent non-Michaelis-Menten type process in the phagocytosis of macrophages in the reticuloendothelial system.

We have developed an embedded stacked DRAM technology that is integrated with 0.2 p n CMOS logic and 6 level metalization. DRAM-based fabrication process enables a memory cell size of 0.405 pm2 with a 0.23 pm design rule. This technology will enable a system-on-a-chip (SOC) with more than 100 Mbits of DRAM capacity on a practical chip size.