O manejo adequado dos recursos naturais em ambientes frágeis, como o da Caatinga, requer o conhecimento de suas propriedades e distribuição espacial. Nesse contexto, o trabalho tem por objetivo avaliar o desempenho de dois algoritmos baseados em aprendizado de máquina (Multi Layer Perceptron (MLP) e o Support Vector Machine (SVM)) e do método da Máxima Verossimilhança na classificação do uso e cobertura da terra no bioma Caatinga. Para o experimento, foi utilizada uma imagem do satélite LANDSAT-5/TM contendo a área de estudo localizada no município de Iguatu-CE e definidas as classes de cobertura da terra, a saber: antropização por agricultura (APA), outros tipos de antropização (OTA), água, caatinga herbácea arbustiva (CHA) e caatinga arbórea densa (CAD). O desempenho dos métodos foi analisado através dos coeficientes de Exatidão Global (EG), Exatidão Específica (EE) e Kappa (K) calculados a partir dos dados da matriz de confusão correspondente à verdade terrestre. Os valores do coeficiente de EG foram de: 86,03%, 82,14% e 81,2% e K de: 0,77, 0,76 e 0,75 nos métodos SVM, MLP e Máxima Verossimilhança, respectivamente. Os valores de EE foram superiores a 70% para todos os classificadores testados. Os resultados obtidos demonstram que os métodos SVM e MLP estão aptos à classificação dos padrões propostos, já que apresentaram resultados semelhantes ao método tradicional da Máxima Verossimilhança. Porém, estes classificadores podem consumir mais tempo na etapa de definição dos parâmetros da rede e de processamento.
This paper presents a low power near real-time pattern recognition technique based on Mathematical Morphology-MM implemented on FPGA (Field Programmable Gate Array). The key to the success of this approach concerns the advantages of machine learning paradigm applied to the translation invariant template-matching operators from MM. The paper shows that compositions of simple elementary operators from Mathematical Morphology based on ELUTs (Elementary Look-Up Tables) are very suitable to embed in FPGA hardware. The paper also shows the development techniques regarding all mathematical modeling for computer simulation and system generating models applied for hardware implementation using FPGA chip. In general, image processing on FPGAs requires low-level description of desired operations through Hardware Description Language-HDL, which uses high complexity to describe image operations at pixel level. However, this work presents a reconfiguring pattern recognition device implemented directly in FPGA from mathematical modeling simulation under Matlab/Simulink/System Generator environment. This strategy has reduced the hardware development complexity. The device will be useful mainly when applied on remote sensing tasks for aerospace missions using passive or active sensors.
Summary In this paper, we present the design of a fully digital binary phase shift keying demodulator for application in satellite high‐rate suppressed carrier telecommand system. The proposed system digitalizes the received signal in the intermediate frequency stage using bandpass sampling technique, and the resulting baseband signal is used to synchronization of symbol and phase and to bit detection. The design of all functional modules is presented in details. Another innovation presented in this work is the inclusion of a non‐linearity in the phase synchronizer module to permit its operation independent from the signal amplitude. Moreover, aiming the characterization and performance evaluation of the system, we do some original mathematical analyses. Finally, test results show that the demodulator complies all the project requirements, and the prototype implementation loss, in terms of bit energy to noise power density ratio, is less than 0.3 dB. Copyright © 2016 John Wiley & Sons, Ltd.
This paper presents the design of a coherent GMSK demodulator, with fully digital architecture, aimed at high speed (10 Mbps) space telemetry applications in which the absolute Doppler offset may reach up to 200 kHz. All functional modules that compose the demodulator are described through block diagrams and mathematical equations. The calculations for the determination of several design parameters are presented. The carrier phase and the symbol timing recovery modules are distinct from those found in the literature for this application and, therefore, original mathematical analysis for the project of such modules are performed. The performance of the proposed GMSK demodulator is evaluated via computational simulation. Besides the bit error rate under several operating conditions, the variance of the estimated parameters by the symbol and carrier synchronizers are measured and compared with theoretical bounds. The main results from computational simulations are presented and demonstrate remarkable performance of the designed demodulator.
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