Modern reconfigurable devices such as FPGAs can be reconfigured at run time. Some of them can be dynamically partially reconfigured, which means part of the FPGA is changed without interrupting other parts. This feature adds tremendous flexibility to the Reconfigurable Computing (RC) Field but also introduces challenges. Reconfigurable Operating Systems tend to ease applications development and most importantly applications verifications and maintenance. In this paper we propose novel scheduling algorithms for reconfigurable computing that can handle both hardware and software tasks. The algorithms proposed reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software/hardware, and give priority to hardware tasks. Results obtained indicate that adding a software processor element not only adds flexibility, but also increases system performance. Two on-line schedulers were designed and implemented. RCSched-I is a simple based implementation that nominates the first available free Partial Reconfigurable Region (PRR) for new tasks. RCSched-II on the other hand nominates any free PRR. Both schedulers check the nominated PRR(s) against the ready task for a match, then decide if there is a need for reconfiguration or not. RCSched-II reconfigures the least recently configured PRR, which increases hardware tasks reuse and decreases total processing time.
A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35μm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator and a D flip-flop having 16% fill-factor and 30μmx26μm dimensions. The multisampling architecture requires only a 1 bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The advantage is that the number of transistors in the pixel is low, saving area and providing higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operation in video mode with 10 bits. Also, we present analysis for the impact of comparator offset voltage in the fixed pattern noise.
Micro-and nanostructures with a tapered sidewall profile are important for antireflection and light trapping applications in solar cell, light emitting diode, and photodetector/imager. Here, the authors will show two etching processes that offer a large taper angle. The first process involved a maskless etching of pre-etched silicon structures having a vertical profile, using a recipe that would give a vertical profile when masked. The authors obtained a moderate taper angle of 14 using CF 4 /O 2 etching gas. The second process involved a one-step etching step with Cr as mask using a recipe that was drastically modified from a nonswitching pseudo-Bosch process that gives a vertical profile. The gas flow ratio of C 4 F 8 /SF 6 was greatly increased from 38/22 to 59/1 to result in a taper angle of 22. Further reduction of the RF bias power led to an unprecedented large taper angle of 39 (at the cost of greatly reduced etching rate), which is even higher than the angle obtained by anisotropic wet etching of silicon. V
In nanofabrication, use of thin resist is required to achieve very high resolution features. But thin resist makes pattern transferring by dry etching difficult because typical resist has poor resistance to plasma etching. One widely employed strategy is to use an intermediate hard mask layer, with the pattern first transferred into this layer, then into the substrate or sublayer. Cr is one of the most popular hard etching mask materials because of its high resistance to plasma etching. Cr etching is carried out in O 2 and Cl 2 or CCl 4 environment to form the volatile etching product CrO 2 Cl 2 , but addition of O 2 gas leads to fast resist etching. In this work, the authors show that Cr 2 O 3 can be etched readily in a Cl 2 /O 2 gas mixture with less oxygen than needed for Cr etching, because Cr 2 O 3 contains oxygen by itself. Thus it is easier to transfer the resist pattern into Cr 2 O 3 than into Cr. For the subsequent pattern transferring into the substrate here silicon using nonswitching pseudo-Bosch inductively coupled plasma-reactive ion etching with SF 6 /C 4 F 8 gas and Cr or Cr 2 O 3 as mask, it was found that the two materials have the same etching resistance and selectivity of 100:1 over silicon. Therefore, Cr 2 O 3 is a more suitable hard mask material than Cr for pattern transferring using dry plasma etching.
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