This paper presents a multi-band low-noise amplifier (LNA) in the 45-nm CMOS silicon-on-insulator (SOI) process. The LNA consists of three stages, with the differential cascode amplifier as the core structure. The first stage is mainly responsible for input matching to ensure favourable noise characteristics and bandwidth, while the subsequent stages increase the gain. Moreover, the LNA utilizes baluns for input/output and interstage impedance matching. Switch capacitances are added to switch the three operating bands of the LNA, which cover 17–38 GHz overall. Measurement results show that the proposed LNA achieves a gain (S21) of 23.0 dB and a noise figure (NF) of 4.0 dB.
This paper presents a differential 19.6–39.4 GHz broadband low-noise amplifier (LNA) in 65-nm CMOS technology. The LNA consists of two cascode stage and one common-source stage. To achieve a wide bandwidth and low average noise figure, inter-stage peak-gain distribution technique and transformer-based triple-coupled technique are developed. Besides, a new compact T-coil-based network is proposed to neutralize the parasitic capacitors and enlarge the gain. The measure results show that the 3-dB bandwidth is from 19.6 to 39.4 GHz, the maximum gain is 23.5 dB, and the noise figure (NF) is from 3.7 to 5.8 dB. The dc power comsumption is 46 mW with 1V supply voltage. The input P1dB is −17 dBm at 30 GHz.
A circulator, which is a non-reciprocal device, is widely used in full-duplex systems, future communication and sensing networks, and quantum computing, and it is difficult to implement a passive topology on a chip. Based on switch-based spatio-temporal conductivity modulation, in this study, we design and implement a non-magnetic on-chip passive circulator operating at the Ku band in a 90-nm bulk CMOS technology using a 25% duty-cycle I/Q clock signal. With the virtue of the four-phase non-overlapping clock signal, the proposed circulator achieves a 3.9 dB transmitter (TX)-to-antenna (ANT) and a 4.0 dB ANT-to-receiver (RX) insertion loss with a 1-dB bandwidth of 2.7 GHz (21.4%). The TX-to-RX isolation is better than 17.2 dB, and the TX-to-ANT IIP3 and ANT-to-RX IIP3 are 19.7 dBm and 20.0 dBm, respectively, while occupying a die area of 1.55 mm × 1.15 mm. Although low-cost bulk CMOS technology is used, competitive isolation, linearity performance, and isolation bandwidth are achieved in the proposed design.
This paper presents a multi-band ultra-low power (ULP) receiver with N-Path Switched-Capacitor (NPSC) networks in 90 nm CMOS process. The NPSC is integrated into the feedback loop of the low noise amplifier (LNA) to flexibly provide narrowband input matching at multiple sub-GHz Industrial, Scientific, and Medical (ISM) bands by adjusting the switching frequency. Moreover, the LNA with an NPSC network is utilized to suppress the out-of-band signal at the input and output of the LNA, simultaneously. In order to achieve an ultra-low power consumption, a sub-threshold LNA and four passive NPSC mixers are implemented in this receiver. The ULP receiver achieves a measured gain of 40±2 dB in ISM bands (430/860/915/960 MHz). The measured noise figure and out-of-band IIP3 are 10±0.5 dB and −0.3±2 dBm, respectively. The ULP receiver chip consumes 320 μW at 0.4 V power supply and occupies a chip area of 0.31 mm2.
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