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LDPC code is a preferred channel code used in modern communication because of its robustness to mitigate the huge noise. In this paper, LDPC with four decoder types is combined with Differential Chaos Shift Keying (DCSK) communication system under AWGN channel. The system is simulated using MATLAB program version 2019a with various amounts of half spreading factor, β ∈ {8, 16, and 32}. The results show that a coding gain is achieved in a range of (1.3-4.6) dB between the coded and uncoded DCSK system. Also, log domain decoder is the best decoder among all types, while hard decision bit flipping decoder appears the worst case in contrast with its simplicity.

Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs high data rate with very low BER.

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