This work aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects at chip level. We first simulate the electric response of future electrical interconnects considering the reduction of the CMOS feature size λ λ λ λ from 0.7 to 0.05 µ µ µ µm. We also consider the architectural evolution of chips to analyze the latency issues. We conclude that: 1) It does not seem necessary in the future chips to consider the integration of optical interconnects (OI) over distances shorter than 1000-2000 λ, λ, λ, λ, because the performance of electric intercomnects is sufficient. 2) The penetration of OIs over distances longer than 10 4 λ λ λ λ could be envisaged (on the sole basis of the performance limitation) provided that it will be possible to demonstrate new generations of (cheap and CMOS-compatible) low-threshold high-efficiency VCSELs and ultra-fast high-efficiency photodiodes. 3) The first possible application of onchip OIs is likely not for inter-block communication but for clock distribution as the energy constraints (imposed by the evolution of CMOS technology) are weaker and because the clock tree is an extremely long interconnect.
We simulated and compared optical and electrical interconnects for intrachip communications, focusing particularly on the dependence of the power consump tion versus the interconnect length and the transmis sion throughput. We conclude that optoelectronic interconnects today consume less energy when the interconnect length is (typically) longer than (2-3) mm. The competition is clearly open in the future. Optical interconnects might contribute to solve onchip power consump tion and crosstalk issues, provided that their technology becomes cheap, compatible with the CMOS processes, and that it will be possible to reduce the threshold current of the VCSEL emitters down to a few µAmps.
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