Definitions and criteria for "resolution" and "resolution enhancement" are discussed, and the primary resolution enhancement techniques (RETs) of OPC, PSM and OAI are categorized according to their control of the fundamental properties of a wave: amplitude, phase, and direction. The history of the invention and development of each of these techniques is then reviewed.Modern RETs are generally combinations of these primary RETs, leading to increased complexity in RET recipes. CAD tools have evolved to cope with this increased complexity. Although these existing RET solutions may allow optical lithography be extended as far as the 32nm IC node, even more capability may be developed if the fourth variable of an electromagnetic wave, polarization, can be exploited as an additional primary RET as well.This manuscript is adapted from a transcript of the SPIE Microlithography plenary session, Feb. 23, 2004.
With the adoption of various combinations of resolution enhancement techniques (RET) for IC lithography, different process constraints are placed on the IC layout. The final layout used for mask production is dramatically different than the original designer's intent. To insure that EDA tools developed for applying RET techniques can have optimal performance, layout methodology must change to create a true "target" layer that represents the actual design intent. Verification of the final layout is then expanded from LVS and DRC to also include lithography process simulation, which compares results to this desired "target" and governs the application of RET.
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