We present a systematic investigation of the oxidation properties of Si dots fabricated on a silicon-on-insulator ͑SOI͒ wafer. Dots with diameters varying from 9 to 81 nm were structured on a SOI wafer. These dots were oxidized in a dry oxygen atmosphere at 700, 850, and 1000°C. The resulting structures were investigated using a side view transmission electron microscopy ͑TEM͒ technique in combination with energy filtered TEM. The dimensions of the residual Si and the grown SiO 2 were then extracted from the micrographs and analyzed. The oxidation appears to be retarded as compared to the well-known planar oxidation. At 700 and 850°C a self-limiting effect is observed as well as a clear pattern dependent oxidation at 850 and 1000°C. We attribute these effects to stress buildup in the oxide. The critical stress, causing the self-limiting effect, is calculated using a model that considers the decrease of the reaction rate with increasing stress perpendicular to the Si surface.

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Uniformly doped single electron transistors nominally consisting of a single island and two silicon tunneling barriers have been fabricated on silicon–on–insulator material. Two operation regimes are found depending upon the gate voltages applied. The structure acts either as a multiple tunnel junction device or as a single electron transistor consisting of a single dot corresponding to the geometrical shape of the device. The multiple tunnel junction behavior is attributed to the formation of additional tunneling barriers, introduced into the structure by the high doping level. We demonstrate that these barriers can be removed by raising the Fermi level via the application of an appropriate gate voltage.

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