SRAM based reprogrammable FPGAs are sensitive to radiation-induced Single Event Upsets (SEU), not only in their user flip-flops and memory, but also in the configuration memory. Appropriate mitigation has to be applied if they are used in space, for example the XTMR scheme implemented by the Xilinx TMRTool and configuration scrubbing. The FLIPPER fault injection platform, described in this paper, allows testing the efficiency of the SEU mitigation scheme. FLIPPER emulates SEU-like faults by doing partial reconfiguration and then applies stimuli derived from HDL simulation (VHDL/Verilog test-bench), while comparing the outputs with the golden pattern, also derived from simulation. FLIPPER has its Device-Under-Test (DUT) FPGA on a mezzanine board, allowing an easy exchange of the DUT device. Results from a test campaign are presented using a design from space application and applying various levels of TMR mitigation.

A fault injection tool for Virtex FPGAs based on the fault emulation technique is presented. It allows to inject faults in the configuration control mechanism differently from the tools developed so far, which address only configuration memory cells and user registers. This permits a more realistic and complete study of device behaviour, especially in those applications in which the system operating in a harsh environment undergoes frequent reconfigurations. Injection is performed by modifying the configuration bitstream while this is loaded into the device, without using standard synthesis tools or available commercial software, such as Jbits or similar. This makes our tool independent of the system used for design development and allows a quick fault injection. Moreover, any register of the configuration state machine can be accessed and the effect of SEUs on them analyzed. This analysis is fundamental before performing radiation ground testing of this kind of devices.

This paper presents a strategy of investigation of SEU upset mechanisms in the configuration logic of Virtex I devices. Measurement procedures specifically addressing configuration logic and a hardware set up for radiation testing are described. The results of a heavy ion radiation test are then presented. Previously unreported failure mechanisms have been observed and classified and their corresponding cross sections measured.Index Terms-Field programmable gate arrays (FPGA), heavy ion radiation effects, radiation effects, semiconductor device radiation testing, single event effects.

No abstract

Reliability is a major concern for electronic circuits, especially for those that operate in harsh environments. One source of problems are Single Event Upsets (SEU), which change the value of flip flops and memory cells. SEUs are a major issue for SRAMbased Field Programmable Gate Arrays (FPGAs), as they may alter the circuit functionality, creating errors that will only be removed if the device is reprogrammed. The cost of traditional techniques to deal with SEUs, like triplication, can be excessive in some applications. One example are Space systems, in which power consumption and weight are limited. In those cases, the use of ad hoc protection techniques that can reduce the cost is interesting. In this paper, new protection techniques for adaptive equalizers implemented in SRAM-based FPGAs are presented. The proposed techniques use the knowledge of the equalizer to provide effective protection at a lower cost. The results show a reduction of up to 70% in the use of resources in comparison to the commercial XTMR solution.Index Terms-Adaptive filters, design cross-section, fault injection, field programmable gate array (FPGA), single event effects.