With an ever-increasing number of frequency bands supported by cellular transceivers (TRX), front-end (FE) complexity increases due to a large number of external SAW filters. The challenge of removing inter-stage filters from multiband 3G receivers (RX) resides in the additional noise contribution due to limited transmitter (TX) leakage rejection at the RX input, intermodulation (IM) products and cross-compression due to TX leakage and strong out-ofband blockers. Increased downconverter dynamic range is thus required for a SAW-less RX path. In addition, avoiding SNR degradation from reciprocal mixing imposes additional constraints on LO phase noise.The presented transceiver ( Fig. 6.2.1) integrates all RX and TX functions required to support a tri-band WCDMA/HSPA (bands I-VI, VIII, IX) and quadband GSM/GPRS/EDGE application in a single chip.The transmit section uses two separate paths: one for EGPRS (polar modulation) and another one for WCDMA (direct conversion). Compared to previously published work [1][2][3], this TRX provides a higher integration level, yielding a superior flexibility in the application and a lower bill-of-materials (BOM).The circuit employs a 2-metal passive integration technology (PICS) allowing the integration of high-Q LNA degeneration inductors, TX matching networks, PLL filters and high-density supply-decoupling capacitors. The active (10mm²) and passive (40mm²) die are double-flip-chip mounted into a 56-pin package. In order to improve the isolation between RX and TX paths (operating simultaneously in 3G mode), octagonal-shaped VCO inductors are used with mutually-orthogonal orientations to achieve better than 95dB isolation between RX and TX VCOs. RX input and TX output paths are routed orthogonally to further minimize the RF coupling. Figure 6.2.2 shows the FE architecture, comprising seven single-ended gainswitchable LNAs (three in 3G and four in 2G). A double-cascode structure provides high isolation between inputs and minimum group-delay change when switching between high and low gain (-16dB) modes. The LNA degeneration inductors are implemented in Al-metal on the passive substrate (PICS), with typical inductance/Q-factor values of 0.7nH/20 at 2GHz and 2.3nH/18 at 1GHz. In 2G mode, each pair of high/low-band LNAs employs a shared degeneration inductor to save area. The LNA output currents are combined in a 2 nd -level cascode circuit and passed through to the RX balun primary coil. Large PMOS devices are used to configure this inductance between low-and high-band settings, with transfer ratios of 6:4/4:3 in high/low band, respectively. The interstage frequency response is tuned per band using a capacitance DAC. The LNA output-current signal is AC coupled to the downconverter core via the balun secondary winding. This effectively prevents LNA even-order distortion components from entering the downconverter stage. The balun output current circulates through two identical current commutators, consisting of transistors Q1, Q2, and Q1′, Q2′ respectively. In high-band operation, the ove...
This paper describes the implementation of a 5:th order complex polynomial predistorter chip in CMOS for linearization of RF power amplifiers. The architecture chosen allows operation either at baseband or IF. The chip was implemented in a 0.8 pm CMOS process and operates at 3.3V supply voltage with 60 mW power consumption. The special architecture of the polynomial predistorter is exploited to reduce the complexity and current consumption of individual blocks. Two-tone measurements performed at an IF of 200 MHz demonstrates that third order intermodulation products can be suppressed by more than 30 dB.
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