Abstract-Recent innovations in software defined CMOS radio transceiver architectures heavily rely on high linearity switched-RC sampler and passive-mixer circuits, driven by digitally programmable multi-phase clocks. Although seemingly simple circuits, the frequency domain analysis of these Linear Periodically Time Variant (LPTV) circuits is often deceptively complex. This paper uses the properties of sampled LPTV systems and the adjoint (inter-reciprocal) network to greatly simplify the analysis of the switched-RC circuit. We first derive the transfer function of the equivalent linear time-invariant filter relating the input to the voltage sampled on the capacitor in the switched-RC kernel. We show how a leakage resistor across the capacitor can easily be addressed using our technique. A signal-flow graph is then developed for the complete continuous-time voltage waveform across the capacitor, and simplified for various operating regions. We finally derive the noise properties of the kernel. The results we derive have largely been reported in prior works, but the use of the adjoint network simplifies the derivation, while also providing circuit insight.

Abstract:A 4-element LO-phase shifting phased-array system with 8-phase passive mixers terminated by baseband capacitors is realized in 65nm CMOS. The passive mixers upconvert both the spatial and frequency domain filtering to RF, realizing blocker suppression directly at the antenna input. 3rd harmonic reception is used to widen the frequency range to 0.6-3.6GHz at 68-195mW power dissipation. Up to +10dBm of P 1dB for out-of-beam/band, a 1-element NF of 3-6dB and in-beam/band IIP3=+2..+9dBm are measured. 2 TextMulti-antenna transceivers with beam-forming are recently gaining interest also for low GHz frequencies (<6GHz) [1]-[4]. In the antenna beam, (phase shifted) signals from multiple antennas add constructively, improving SNR, while out-of-beam signals add destructively (i.e. spatial filtering).Usually the summation point is behind some gain blocks, which then need to be capable of handling strong signals. To improve the input-referred compression point P 1dB , a fully passive switchedcapacitor approach was presented in [4], providing P 1dB =+2dBm, but at a high noise penalty:NF=18dB. Here we propose to sum immediately at the baseband capacitors of passive mixer-first switched-RC down-converters. We will show that this can render a direction dependent RF impedance (spatial filtering) together with RF band-pass frequency filtering at lower noise and higherThe proposed architecture is shown in Analog G m blocks consume 36mW generating 100mS at I and Q paths. Overall power when 4 elements are activated is 68-195mW for the received frequency range of 0.6-3.6GHz. The maximum ripple in the gain is 2.5dB and in-beam/band IIP3 varies from +2.. +9dBm (see Fig. 5.2.5). The first harmonic is rejected between 15-25dB. The measurement results are compared to three previously reported 4-element phased-array systems. Clearly remarkable P 1dB and NF are achieved, and the dynamic range at the antenna inputs is substantially improved compared to previous work.Acknowledgment:

Multiple-input multiple-output (MIMO) beamforming array gain can make multi-antenna transmitters (TXs) more power efficient. However, these MIMO TXs require more complex digital predistortion (DPD). In this work, analytical expressions are derived for the power consumption of both MIMO power amplifier (PA) arrays and their respective DPD, taking into account the effects of precoding on PA output power and peak-toaverage power ratio (PAPR). It is shown that for complex DPD algorithms such as cross-over DPD (CO-DPD) in combination with wide bandwidths, the overall DPD power consumption can exceed the overall PA power consumption already for TXs for scenarios with more than two antennas.

This paper derives the efficiency limitations of switched capacitor power amplifiers (SCPAs) due to switched capacitor (SC) losses during charging and discharging of their capacitor arrays. Polar modulation is covered, as well as quadrature modulation both with clock duty cycles of 50% (Q50) and 25% (Q25). Closed form expressions are derived for both the maximum output power and SC power loss for signals with arbitrary phase and amplitude. These expressions are verified by simulations using ideal switches and capacitors, and 22 nm CMOS transistor models. These results are used to analyze the SCPA efficiency for 64QAM signals using a statistical model. It is shown that for a given array capacitance and supply voltage, the polar architecture is the most power efficient. Compared to polar modulation, the SC loss for 64QAM is fundamentally 18% higher for Q50 and 46% higher for Q25 SCPAs, whereas the generated output powers are fundamentally 6 and 3dB lower, respectively.

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and non-switching driver cells. Often, digital predistortion (DPD) is required to transmit higher order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of -50 dB and an error vector magnitude (EVM) of -45.5 dB for 5 MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.