This paper described a method to design a limit-cycle suppressor. The dithering technique was used to eliminate self-sustained oscillations or limit cycles. Otherwise, the Dual Input Describing Function (DIDF) method was applied to design dither parameters and analyze the existence of limit cycles. This method was done in a nonlinear system with relay nonlinearity using three standard dither signals, namely sine, triangle, and square waves. The aim of choosing varying dithers was to investigate the effect of dither shapes and the minimum amplitude required for the quenching strategy. First, the possibility and amplitude of limit cycles were determined graphically on the DIDF curve. Then, the minimum amplitude of dither was calculated based on the DIDF analysis. Finally, a simulation was built to verify the analytical work using a digital computer. The simulation results were related to the analysis results. It was evident that the dithering technique is a simple way to suppress limit cycles in a nonlinear system. This paper also presented that dither is an amplitude function, and square-wave dither has the minimum amplitude to quench limit cycles.
Teknologi HCMOS merupakan teknologi CMOS dalam rangkaian terpadu dengan penambahan kaskade inverter. IC flip-flop R-S HCMOS merupakan IC flip-flop R-S CMOS dengan penambahan dua kaskade inverter pada sisi outputnya. Tujuan penelitian ini adalah meningkatkan kecepatan propagation delay IC flip-flop R-S HCMOS mengunakan metode penambahan kaskade inverter. Dengan menambahkan dua kaskade, empat kaskade, dan enam kaskade pada flip-flop R-S HCMOS serta mengatur perbandingan W dan L diharapkan dapat diketahui perubahan kecepatan yang dihasilkan dari flip-flop R-S tersebut. Simulasi yang dilakukan dengan program PSPICE pada suhu 117 0C¬, CL= 15 pF, dan f= 2 MHz menunjukkan bahwa flip-flop R-S HCMOS enam kaskade menghasilkan tPD= 9 kali lebih cepat dan PDP= 9 kali lebih kecil dari flip-flop R-S HCMOS empat kaskade. Sedangkan flip-flop R-S HCMOS empat kaskade menghasilkan tPD = 9 kali lebih cepat dan PDP= 9 kali lebih kecil dari tPD flip-flop R-S HCMOS dua kaskade. Penggambaran layout IC flip-flop R-S HCMOS enam kaskade dengan pada i/o yang dilakukan dengan program Microwind memiliki luasan 2,8 mm x 1,5 mm.
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