We propose a new specification environment for system-level design called ECL. It combines the Esterel and C languages to provide a more versatile means for specifying heterogeneous designs. It can be viewed as the addition to C of explicit constructs from Esterel for concurrency and pre-emption, and thus makes these operations easier to specify and more apparent. An ECL specification is compiled into a reactive part (an extended finite state machine representing most of the ECL program), and a pure data looping part. The first can be robustly estimated and synthesized to hardware or software, while the second is implemented in software as specified. ECL is a good candidate for specification of new behavior in system-level design tools such as Cadence's Cierto VCC tool [l]. ECL is especially targeted for specification of control protocols between data-computing behavioral blocks.
SystemC is a system-level design and simulation language based on Cþþ. We've been using SystemC for computer organization and design projects for the past several years. Because SystemC is embedded in Cþþ it contains the powerful abstraction mechanisms of Cþþ not found in traditional hardware description languages, such as support for object-oriented programming and generic programming (templates). This support for abstraction allows instructors to reinforce standard abstraction concepts such as information hiding, interfaces, and abstract data types, standard fare in a computer science curriculum. Furthermore, embedded software is often written in Cþþ and SystemC provides threading facilities useful for designing and implementing embedded software.
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