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In this paper, we investigate the impact of Ge-enrichment coupled to N-or C-doping in Ge 2 Sb 2 Te 5 based materials on low-resistance state (LRS or SET) performance combined with high-resistance state (HRS or RESET) high-temperature data retention (HTDR) in Phase-Change Memories (PCM). These innovative materials have been integrated in state-of-the-art memory cell prototypes. For the first time, a focus on the trade-off between SET stability (which is affected by resistance drift) and RESET HTDR is proposed. This aspect has been extensively characterized. Through physico-chemical analysis and electrical characterization we demonstrate the need for a specific "programming-current-vs-time-profile" to finally achieve an LRS stable at high-working temperature with programming times compatible with industrial applications. Finally, the reliability of the HRS and the LRS obtained with our optimized programming procedure has been demonstrated through Reflow Soldering Temperature Profile (RSTP) tests. The last result fully enables PCM for embedded applications, in which data integrity after the peak temperature of reflow soldering must be ensured.

To satisfy the growing market demand for embedded non-volatile memory (eNVM), alternative solutions to Flash technology are currently under investigation. Among these, phase change memory (PCM) is attracting strong interest due to the low cost of integration with the CMOS front-end and good scalability. Embedded PCM (ePCM), however, must feature high reliability during both packaging and functional stages. This work studies reliability of PCM based on Ge-rich GeSbTe, providing evidence for resistance drift and decay in both the reset and set states. Set state instability is attributed to grain-boundary relaxation and grain growth. A unified model is presented, capable of predicting the reliability of set/reset states at elevated temperature.

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